1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. NAND and NOR Logic Networks CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff HW2 is due today

4. Administrative Stuff HW3 is out It is due on Monday Sep 16 @ 4pm. Please write clearly on the first page (in block capital letters) the following three things:  Your First and Last Name  Your Student ID Number  Your Lab Section Letter

5. Quick Review

6. x 1 x 2 x 1 x 2 + AND gate x x x 1 x 2 x 1 x 2  The Three Basic Logic Gates [ Figure 2.8 from the textbook ] OR gate NOT gate

7. Truth Table for NOT x x xx 0 1 1 0

8. x 1 x 2 x 1 x 2  Truth Table for AND

9. Truth Table for OR x 1 x 2 x 1 x 2 +

10. DeMorgan’s Theorem

11. Two New Logic Gates

12. NAND Gate x1x1 x2x2 f 001 011 101 110

13. NOR Gate x1x1 x2x2 f 001 010 100 110

14. AND vs NAND x1x1 x2x2 f 001 011 101 110 x 1 x 2 x 1 x 2  x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2 

15. AND followed by NOT = NAND x1x1 x2x2 f 001 011 101 110 x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2  x 1 x 2  f 1 1 1 0 x 1 x 2 x 1 x 2 

16. NAND followed by NOT = AND x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2  x1x1 x2x2 f 001 011 101 110 x 1 x 2  f 0 0 0 1 x 1 x 2 x 1 x 2 

17. OR vs NOR x1x1 x2x2 f 000 011 101 111 x1x1 x2x2 f 001 010 100 110 x 1 x 2 x 1 x 2 +

18. OR followed by NOT = NOR x1x1 x2x2 f 001 010 100 110 x1x1 x2x2 f 000 011 101 111 f 1 0 0 0 x 1 x 2 x 1 x 2 +x 1 x 2 +

19. NOR followed by NOT = OR x1x1 x2x2 f 000 011 101 111 x1x1 x2x2 f 001 010 100 110 f 0 1 1 1 x 1 x 2 x 1 x 2 + x 1 x 2 + x 1 x 2 x 1 x 2 +

20. Why do we need two more gates?

21. They can be implemented with fewer transistors. (more about this later)

22. They are simpler to implement, but are they also useful?

23. Building a NOT Gate with NAND xx 0 1 1 0 x x xx xxf 001 011 101 110

24. xx 0 1 1 0 x x xx xxf 001 011 101 110 impossible combinations

25. Building a NOT Gate with NAND xx 0 1 1 0 x x xx xxf 001 011 101 110 impossible combinations Thus, the two truth tables are equal!

26. Building an AND gate with NAND gates [http://en.wikipedia.org/wiki/NAND_logic]

27. Building an OR gate with NAND gates [http://en.wikipedia.org/wiki/NAND_logic]

28. Implications Any Boolean function can be implemented with only NAND gates!

29. NOR gate with NAND gates [http://en.wikipedia.org/wiki/NAND_logic]

30. XOR gate with NAND gates [http://en.wikipedia.org/wiki/NAND_logic]

31. XNOR gate with NAND gates [http://en.wikipedia.org/wiki/NAND_logic]

33. Building a NOT Gate with NOR xx 0 1 1 0 x x xx xxf 001 010 100 110

34. xx 0 1 1 0 x x xx xxf 001 010 100 110 impossible combinations

35. Building a NOT Gate with NOR xx 0 1 1 0 x x xx xxf 001 010 100 110 impossible combinations Thus, the two truth tables are equal!

36. Building an OR gate with NOR gates [http://en.wikipedia.org/wiki/NOR_logic]

37. Let’s build an AND gate with NOR gates

38. Implications Any Boolean function can be implemented with only NOR gates!

39. NAND gate with NOR gates [http://en.wikipedia.org/wiki/NOR_logic]

40. XOR gate with NOR gates [http://en.wikipedia.org/wiki/NOR_logic]

41. XNOR gate with NOR gates [http://en.wikipedia.org/wiki/NOR_logic]

42. The following examples came from this book

43. [ Platt 2009 ]

46. DeMorgan’s theorem in terms of logic gates x 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 += (a) x 1 x 2

47. DeMorgan’s theorem in terms of logic gates x 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 + x 1 x 2 = (b)

48. Function Synthesis

49. Using NAND gates to implement a sum-of-products [ Figure 2.27 from the textbook ]

50. Using NOR gates to implement a product-of sums [ Figure 2.28 from the textbook ]

51. Example 2.13

52. NOR-gate realization of the function x1x1 f (a) POS implementation (b) NOR implementation f x3x3 x2x2 x1x1 x3x3 x2x2 [ Figure 2.29 from the textbook ]

53. Example 2.10

54. NAND-gate realization of the function [ Figure 2.30 from the textbook ] f f (a) SOP implementation (b) NAND implementation x1x1 x3x3 x2x2 x3x3 x2x2 x1x1

56. Appendix B Implementation Technology

57. Figure B.1. Logic values as voltage levels.

58. Figure B.2. NMOS transistor as a switch. DrainSource x = "low"x = "high" (a) A simple switch controlled by the inputx V D V S (b) NMOS transistor Gate (c) Simplified symbol for an NMOS transistor V G Substrate (Body)

59. Figure B.3. PMOS transistor as a switch. Gate x = "high"x = "low" (a) A switch with the opposite behavior of Figure 3.2a V G V D V S (b) PMOS transistor (c) Simplified symbol for a PMOS transistor V DD DrainSource Substrate (Body)

60. (a) NMOS transistor V G V D V S = 0 V V S =V DD V D V G Closed switch whenV G =V DD V D = 0 V Open switch whenV G = 0 V V D Open switch whenV G =V DD V D V Closed switch whenV G = 0 V V D =V DD V (b) PMOS transistor Figure B.4. NMOS and PMOS transistors in logic circuits.

61. (b) Simplified circuit diagram V x V f V DD xf (c) Graphical symbols xf R V x V f R + - (a) Circuit diagram 5 V Figure B.5. A NOT gate built using NMOS technology.

62. Figure B.6. NMOS realization of a NAND gate. V f V DD (a) Circuit (c) Graphical symbols (b) Truth table ff 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f V x 2 V x 1 x 1 x 2 x 1 x 2

63. Figure B.7. NMOS realization of a NOR gate.

64. Figure B.8. NMOS realization of an AND gate. (a) Circuit (c) Graphical symbols (b) Truth table f f 0 0 1 1 0 1 0 1 0 0 0 1 x 1 x 2 f V f V DD A V x 1 V x 2 x 1 x 2 x 1 x 2 V

65. Figure B.9. NMOS realization of an OR gate.

66. Figure B.10. Structure of an NMOS circuit.

67. Figure B.11. Structure of a CMOS circuit.

68. Figure B.12. CMOS realization of a NOT gate. (a) Circuit V f V DD V x (b) Truth table and transistor states on off on 1 0 0 1 fx T 1 T 2 T 1 T 2

69. Figure B.13. CMOS realization of a NAND gate.

70. Figure B.14. CMOS realization of a NOR gate.

71. Figure B.15. CMOS realization of an AND gate.

73. NAND and NOR gates with n inputs [ Figure 2.25 from the textbook ]

74. Figure B.57. High fan-in NMOS NAND gate.

75. Figure B.58. High fan-in NMOS NOR gate. x k V f V DD V x 1 V x 2 V

76. Questions?

77. THE END