1. SecurOne - Design Presentation Group M1 Insik Yoon Mehul Jain Sriteja Tangeda Umang Shah Secure unique Smart Card and Card Reader Monday 26 th October Layouts of Modules

2. Status Finished: – Design selections – Block diagram for processes – Behavioral Verilog – Behavioral Verilog Simulations – Floorplan – Structural Verilog Simulations – Schematic and Simulations(Individual blocks and FSMs) – Layout (Individual Modules) To Do: – Testing – Simulation

3. D Flip Flop

4. XOR Gate

5. Mux 2:1

6. OR Gate

7. NAND 2 Gate

8. 0 1 CLK D D Card_insert Card_read, Fp_read Dec_complete 10 Reset CLK 8 BIT COUNTER Dec_complete D CLK SRAM WE WL Freq Divider Comparator To Menu FSM 16 Bit data Initial FSM

9. Cadence Schematic

10. Simulation Waveforms

11. Waveforms Contd

12. CLK From Main Menu DISPLAY CLK 5 Bit Choice Reg-file Display 5 WE Q_b Q Q OR rd FP_SRAM 4B W1 W2 W3 W4 WL Central Server 16 D 1 0 Reset CLK 8 BIT COUNTER Encryptor CLK 16 Central_Com plete W5 W6 W7 QQ CLK W8 Update_Com plete Update FSM 5 To Central Server 16 To Smart Card WE To Smart Card

13. Cadence Schematic

14. Simulation Waveforms

15. Waveforms Contd

17. CLK From Main Menu DISPLAY CLK 5 Bit Choice Reg-file Update 5 WE Q_b Q Q rd W1 W2 W3 W4 Smart Card D 1 0 Reset CLK 8 BIT COUNTER Decryptor CLK 16 Smart_Card_ Ready W5 W6 W7 QQ CLK W8 Display/Trans action_Compl ete Display/Transaction FSM 5 Q CLK We_SC 16 To Display/Transac tion SRAM WE To Display/Trans action SRAM

18. Cadence Schematic

19. Simulation Waveform

20. Waveforms Contd

22. OR GATE Comparator_Complete Update_Complete Display_Complete Trans_Complete Exit’ W1 0 1 DISPLAY 2 to 4 Decoder 2 Update Trans Display Exit Main FSM

23. Cadence Schematic

24. Waveforms Contd

25. Clock Generator Schematic

26. UMANG

27. SRAM 1 BIT

28. WRITE DRIVER

29. BITLINE PRECHARGE CIRCUIT

30. SKEWED INVERTERS

31. 32 BIT REGFILE

32. 16 BIT REGFILE

33. 5 BIT REGFILE

34. INSIK

35. 1 BIT FULL ADDER

36. 8 BIT FULL ADDER

37. 2 x 4 DECODER

38. 2 I/P XOR

39. 4 I/P XOR

40. FREQUENCY DIVIDER

41. FREQUENCY DIVIDER SIMULATION

42. MEHUL

43. 2 x 1 MUX

44. 2 x 1 MUX SIMULATION

45. HLFF

46. HLFF SIMULATION

47. MODULO 8 COUNTER

48. COUNTER SIMULATION

49. LOAD REGISTER

50. SRITEJA

51. VoV1 V0<<<4V0>>>5V1>>>5V1<<<4 32-bit key reg 8-bit Adder K2 K0K3K1 88 88 8-bit Adder/sub Counter Complete

52. 2 I/P AND

53. 2 I/P OR

54. 3 I/P AND

55. 2 x 1 MUX

56. Encryptor Decryptor 4 B SRAM Comparator Choice Regfile Display SRAM 2B Trans. SRAM 2B Update FSM Display FSM Trans. FSM Initial FSMExit Main Menu FSM W1 W2 R2 Decryption_complete R1 Decrypted_Data FP_1 Compare_result 2 Write 16 FP_2 16 choice Read Display_menu 2 2 2 choice 1 1 1 return exit R1 Write Read Write Read encryption_complete Write Read FLOOR-PLAN

57. Transistor Counts BlockTransistor Count Encryption/Decryption 8000 FSMs (Including SRAMS) 3616 Comparator 620