1. George Mason University ECE 545 – Introduction to VHDL Data Flow & Structural Modeling of Combinational Logic ECE 545 Lecture 2

2. 2ECE 545 – Introduction to VHDL Resources Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 1, VHDL Fundamentals Chapter 2, Getting Your First Design Done Chapter 3, Gates, Decoders and Encoders Chapter 9, Design Partitioning (Design Hierarchy, Hierarchy in VHDL) Peter J. Ashenden, The Designer’s Guide to VHDL Chapter 1, Fundamental Concepts

3. 3ECE 545 – Introduction to VHDL Register Transfer Logic (RTL) Design Description Combinational Logic Combinational Logic Registers … Today’s Topic

4. 4ECE 545 – Introduction to VHDL VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers State machines Test benches Sequential statements Subset most suitable for synthesis

5. 5ECE 545 – Introduction to VHDL VHDL Fundamentals

6. 6ECE 545 – Introduction to VHDL Naming and Labeling (1) VHDL is not case sensitive Example: Names or labels databus Databus DataBus DATABUS are all equivalent

7. 7ECE 545 – Introduction to VHDL Naming and Labeling (2) General rules of thumb (according to VHDL-87) 1.All names should start with an alphabet character (a-z or A-Z) 2.Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) 3.Do not use any punctuation or reserved characters within a name (!, ?,., &, +, -, etc.) 4.Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid) 5.All names and labels in a given entity and architecture must be unique

8. 8ECE 545 – Introduction to VHDL Free Format VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b)then or if (a = b) then are all equivalent

9. 9ECE 545 – Introduction to VHDL Readability standards ESA VHDL Modelling Guidelines published by European Space Research and Technology Center in September 1994 available at the course web page

10. 10ECE 545 – Introduction to VHDL Readability standards Selected issues covered by ESA Guidelines: Consistent Writing Style Consistent Naming Conventions Consistent Indentation Consistent Commenting Style Recommended File Headers File naming and contents Number of statements/declarations per line Ordering of port and signal declarations Constructs to avoid

11. 11ECE 545 – Introduction to VHDL Comments Comments in VHDL are indicated with a “double dash”, i.e., “--”  Comment indicator can be placed anywhere in the line  Any text that follows in the same line is treated as a comment  Carriage return terminates a comment  No method for commenting a block extending over a couple of lines Examples: -- main subcircuit Data_in <= Data_bus; -- reading data from the input FIFO

12. 12ECE 545 – Introduction to VHDL Comments Explain Function of Module to Other Designers Explanatory, Not Just Restatement of Code Locate Close to Code Described Put near executable code, not just in a header

13. 13ECE 545 – Introduction to VHDL Modeling wires and buses

14. 14ECE 545 – Introduction to VHDL Signals signal A : std_logic; signal B : std_logic_vector(7 downto 0); wire A bus B 1 8

15. 15ECE 545 – Introduction to VHDL Standard Logic Vectors signal A: STD_LOGIC; signal B: STD_LOGIC_VECTOR(3 downto 0); signal C: STD_LOGIC_VECTOR(3 downto 0); signal D: STD_LOGIC_VECTOR(7 downto 0); signal E: STD_LOGIC_VECTOR(15 downto 0); signal F: STD_LOGIC_VECTOR(8 downto 0); ………. A <= ‘1’; B <= ”0000”; -- Binary base assumed by default C <= B”0000”; -- Binary base explicitly specified D <= ”0110_0111”; -- You can use ‘_’ to increase readability E <= X”AF67”; -- Hexadecimal base F <= O”723”; -- Octal base

16. 16ECE 545 – Introduction to VHDL Describing Combinational Logic Using Dataflow Design Style

17. 17ECE 545 – Introduction to VHDL Data-flow VHDL concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements

18. 18ECE 545 – Introduction to VHDL Data-flow VHDL concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements

19. 19ECE 545 – Introduction to VHDL Data-flow VHDL: Example

20. 20ECE 545 – Introduction to VHDL Data-flow VHDL: Example LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT (x, y, Cin: IN STD_LOGIC ; s, Cout: OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ;

21. 21ECE 545 – Introduction to VHDL Logic Operators Logic operators Logic operators precedence and or nand nor xor not xnor not and or nand nor xor xnor Highest Lowest

22. 22ECE 545 – Introduction to VHDL Wanted: Y = ab + cd Incorrect Y <= a and b or c and d equivalent to Y <= ((a and b) or c) and d equivalent to Y = (ab + c)d Correct Y <= (a and b) or (c and d) No Implied Precedence

23. 23ECE 545 – Introduction to VHDL Concatenation signal A: STD_LOGIC_VECTOR(3 downto 0); signal B: STD_LOGIC_VECTOR(3 downto 0); signal C, D, E: STD_LOGIC_VECTOR(7 downto 0); A <= ”0000”; B <= ”1111”; C <= A & B; -- C = ”00001111” D <= ‘0’ & ”0001111”; -- D <= ”00001111” E <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- E <= ”00001111”

24. 24ECE 545 – Introduction to VHDL Rotations in VHDL A(3) A(2) A(1) A(0) A(2)A(1)A(0)A(3) A<<<1 A_rotL <= A(2 downto 0) & A(3)

25. 25ECE 545 – Introduction to VHDL Arithmetic Functions in VHDL (1) To use basic arithmetic operations involving std_logic_vectors you need to include the following library packages: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

26. 26ECE 545 – Introduction to VHDL Arithmetic Functions in VHDL (2) You can use standard +, - operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C <= A + B;

27. 27ECE 545 – Introduction to VHDL Data-flow VHDL concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements

28. 28ECE 545 – Introduction to VHDL Data Flow Instructions (1) target_signal <= value1 when condition1 else value2 when condition2 else... valueN-1 when conditionN-1 else valueN; When - Else.… Value N Value N-1 Condition N-1 Condition 2 Condition 1 Value 2 Value 1 Target Signal …

29. 29ECE 545 – Introduction to VHDL Operators Relational operators Logic and relational operators precedence = /= >= not = /= >= and or nand nor xor xnor Highest Lowest

30. 30ECE 545 – Introduction to VHDL compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else … Priority of logic and relational operators

31. 31ECE 545 – Introduction to VHDL Data-flow VHDL concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements

32. 32ECE 545 – Introduction to VHDL Data Flow Instructions (2) with choice_expression select target_signal <= expression1 when choices1, expression2 when choices2,... expressionN when choicesN; With - Select choices1 choices2 choicesN expression1 target_signal choice expression expression2 expressionN

33. 33ECE 545 – Introduction to VHDL MLU Example

34. 34ECE 545 – Introduction to VHDL MLU: Block Diagram

35. 35ECE 545 – Introduction to VHDL MLU: Entity Declaration library IEEE; use IEEE.STD_LOGIC_1164.all; entity MLU is port( NEG_A : in STD_LOGIC; NEG_B : in STD_LOGIC; NEG_Y : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; L1 : in STD_LOGIC; L0 : in STD_LOGIC; Y : out STD_LOGIC ); end MLU;

36. 36ECE 545 – Introduction to VHDL MLU: Architecture Declarative Section architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0:STD_LOGIC; signal MUX_1:STD_LOGIC; signal MUX_2:STD_LOGIC; signal MUX_3:STD_LOGIC; signal L: STD_LOGIC_VECTOR(1 downto 0);

37. 37ECE 545 – Introduction to VHDL MLU - Architecture Body begin A1<= not A when (NEG_A='1') else A; B1<= not B when (NEG_B='1') else B; Y <= not Y1 when (NEG_Y='1') else Y1; MUX_0 <= A1 and B1; MUX_1 <= A1 or B1; MUX_2 <= A1 xor B1; MUX_3 <= A1 xnor B1; L<=L1 & L0; with (L) select Y1 <= MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;

38. 38ECE 545 – Introduction to VHDL Data-flow VHDL concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements

39. 39ECE 545 – Introduction to VHDL PARITY Example

40. 40ECE 545 – Introduction to VHDL PARITY: Block Diagram

41. 41ECE 545 – Introduction to VHDL For Generate Statement For Generate name: for parameter_specification generate [Declaration Statements] begin {Concurrent Statements} end generate name;

42. 42ECE 545 – Introduction to VHDL PARITY: Entity Declaration library IEEE; use IEEE.STD_LOGIC_1164.all; entity PARITY is port( Parity_in : in STD_LOGIC_VECTOR(7 downto 0); Parity_out : out STD_LOGIC ); end PARITY;

43. 43ECE 545 – Introduction to VHDL PARITY: Block Diagram Xor_out(1) Xor_out(2) Xor_out(3) Xor_out(4) Xor_out(5) Xor_out(6) Xor_out(7)

44. 44ECE 545 – Introduction to VHDL PARITY: Architecture architecture PARITY_DATAFLOW of PARITY is signal Xor_out: std_logic_vector (7 downto 1); begin Xor_out(1) <= Parity_in(0) xor Parity_in(1); G2: for i in 1 to 6 generate Xor_out(i+1) <= Xor_out(i) xor Parity_in(i+1); end generate G2; Parity_out <= Xor_out(7); end PARITY_DATAFLOW;

45. 45ECE 545 – Introduction to VHDL Verifying the operation of the circuit using testbenches

46. 46ECE 545 – Introduction to VHDL Testbench Block Diagram Testbench Processes Generating Stimuli Design Under Test (DUT) Observed Outputs

47. 47ECE 545 – Introduction to VHDL Testbench Defined Testbench applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs. The results can be viewed in a waveform window or written to a file. Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability). The same Testbench can be easily adapted to test different implementations (i.e. different architectures) of the same design.

48. 48ECE 545 – Introduction to VHDL Testbench Anatomy Entity TB is --TB entity has no ports End TB; Architecture arch_TB of TB is --Local signals and constants component TestComp --All Design Under Test component declarations port ( ); end component; ----------------------------------------------------- for DUT:TestComp use entity work.TestComp(archName)--Specify entity/arch pair -- (OPTIONAL) begin testSequence: Process --Main test process end process; DUT:TestComp port map( --Port map all the DUTs ); End arch_TB;

49. 49ECE 545 – Introduction to VHDL Testbench For XOR3 library ieee; use ieee.std_logic_1164.all; entity XOR3_TB is end XOR3_TB; architecture XOR3_TB_ARCHITECTURE of XOR3_TB is -- Component declaration of the tested unit component xor3 port( A : in std_logic; B : in std_logic; C : in std_logic; RESULT : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal TEST_VECTOR:STD_LOGIC_VECTOR(2 downto 0); signal TEST_RESULT: STD_LOGIC;

50. 50ECE 545 – Introduction to VHDL Testbench For XOR Gate(2) begin UUT : xor3 port map ( A => TEST_VECTOR(0), B => TEST_VECTOR(1), C => TEST_VECTOR(2), RESULT => TEST_RESULT); ); TESTING: process begin TEST_VECTOR<="000"; wait for 10 ns; TEST_VECTOR<="001"; wait for 10 ns; TEST_VECTOR<="010"; wait for 10 ns; TEST_VECTOR<="011"; wait for 10 ns; TEST_VECTOR<="100"; wait for 10 ns; TEST_VECTOR<="101"; wait for 10 ns; TEST_VECTOR<="110"; wait for 10 ns; TEST_VECTOR<="111"; wait for 10 ns; end process TESTING; end XOR3_TB_ARCHITECTURE;

51. 51ECE 545 – Introduction to VHDL Execution of statements in a PROCESS The execution of statements continues sequentially till the last statement in the process. After execution of the last statement, the control is again passed to the beginning of the process. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process TESTING; Order of execution Program control is passed to the first statement after BEGIN

52. 52ECE 545 – Introduction to VHDL PROCESS with a WAIT Statement The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait; end process TESTING; Program execution stops here Order of execution

53. 53ECE 545 – Introduction to VHDL Wait for vs. Wait Wait for: waveform will keep repeating itself forever Wait : waveform will keep its state after the last wait instruction. 0 123 … 0 123 …

54. 54ECE 545 – Introduction to VHDL Sequential Statements (3) Loop Statement Repeats a Section of VHDL Code Example: process every element in an array in the same way for i in range loop statements end loop;

55. 55ECE 545 – Introduction to VHDL TEST_DATA_GENERATOR: process begin TEST_AB<="00"; TEST_SEL<="00"; for I in 0 to 3 loop for J in 0 to 3 loop wait for 10 ns; TEST_AB<=TEST_AB+"01"; end loop; TEST_SEL<=TEST_SEL+"01"; end loop; end process; Loop Statement - Example

56. 56ECE 545 – Introduction to VHDL Structural Design Style

57. 57ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

58. 58ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

59. 59ECE 545 – Introduction to VHDL Structural Example: Component NAND2 Instantiated Four Time in1 in2 nand_out

60. 60ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

61. 61ECE 545 – Introduction to VHDL Iterative circuits: 8-bit comparator A(7)B(7) CMP_IN(1) CMP_IN(0) A(6)B(6)A(0)B(0) CMP_OUT(1) CMP_OUT(0) entity COMPARE8 is port( A, B: in STD_LOGIC_VECTOR(7 downto 0); CMP_IN: in STD_LOGIC_VECTOR(1 downto 0); CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0)); end COMPARE8; COMPARE8

62. 62ECE 545 – Introduction to VHDL 8-bit comparator: Truth Table CMP_INCMP_OUT 00 00 if A=B 10 if A>B 01 if A<B 10 10 independently of A and B 01 01 independently of A and B 11 (invalid inputs) --

63. 63ECE 545 – Introduction to VHDL AB X_OUT Y_OUT BIT_COMPARE entity BIT_COMPARE is port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end BIT_COMPARE; X_IN Y_IN Basic building block

64. 64ECE 545 – Introduction to VHDL X_IN & Y_INX_OUT & Y_OUT 00 00 if A=B 10 if A=‘1’ and B=‘0’ 01 if A=‘0’ and B=‘1’ 10 10 independently of A and B 01 01 independently of A and B 11 (invalid inputs) -- Basic building block – Truth Table

65. 65ECE 545 – Introduction to VHDL 8-bit comparator - Architecture A(7)B(7) CMP_IN(1) CMP_IN(0) A(6)B(6)A(0)B(0) CMP_OUT(1) CMP_OUT(0) INT_X(7) INT_X(1) INT_Y(7) INT_Y(1) INT_X(6) INT_Y(6)

66. 66ECE 545 – Introduction to VHDL architecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(7 downto 1); begin C7: BIT_COMPARE port map(A(7), B(7), CMP_IN(1), CMP_IN(0), INT_X(7), INT_Y(7)); C6: BIT_COMPARE port map(A(6), B(6), INT_X(7), INT_Y(7), INT_X(6), INT_Y(6));... C0: BIT_COMPARE port map(A(0), B(0), INT_X(1), INT_Y(1), CMP_OUT(0), CMP_OUT(1)); end STRUCTURE; Architecture without for-generate

67. 67ECE 545 – Introduction to VHDL 8-bit comparator - Architecture A(7)B(7) CMP_IN(1) CMP_IN(0) A(6)B(6)A(0)B(0) CMP_OUT(1) CMP_OUT(0) INT_X(7)INT_X(1) INT_Y(7) INT_Y(1) INT_X(8) INT_Y(8) INT_X(0) INT_Y(0)

68. 68ECE 545 – Introduction to VHDL architecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(8 downto 0); begin INT_X(8) <= CMP_IN(1); INT_Y(8) <= CMP_IN(0); CASCADE: for I in 7 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I), INT_Y(I)); end generate; CMP_OUT(1) <= INT_X(0); CMP_OUT(0) <= INT_Y(0); end STRUCTURE; Architecture with for-generate

69. 69ECE 545 – Introduction to VHDL Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

70. 70ECE 545 – Introduction to VHDL N-bit Comparator – Entity declaration entity COMPAREN is generic(N: positive); -- N – width of operands port( A, B: in BIT_VECTOR(N-1 downto 0); CMP_IN: in BIT_VECTOR(1 downto 0); CMP_OUT: out BIT_VECTOR(1 downto 0)); end COMPAREN;

71. 71ECE 545 – Introduction to VHDL architecture STRUCTURE of COMPAREN is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(N downto 0); begin INT_X(N) <= CMP_IN(1); INT_Y(N) <= CMP_IN(0); CASCADE: for I in N-1 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I), INT_Y(I)); end generate; CMP_OUT(1) <= INT_X(0); CMP_OUT(0) <= INT_Y(0); end STRUCTURE; N-bit Comparator – Architecture

72. 72ECE 545 – Introduction to VHDL component COMPAREN generic(N: positive); -- N – width of operands port( A, B: in STD_LOGIC_VECTOR(N downto 0); CMP_IN: in STD_LOGIC_VECTOR(1 downto 0); CMP_OUT: out STD_LOGIC_VECTOR(1 downto 0)); end component; ……… CMP8: COMPAREN generic map(N => 16) port map(A => P1, B => P2, CMP_IN => SIG_IN, CMP_OUT => SIG_OUT ); N-bit Comparator – Instantiation