1. On the Relation Between Simulation-based and SAT-based Diagnosis CMPE 58Q Giray Kömürcü Boğaziçi University

2. Is it Possible to Design a Circuit with thousands, millions, billions of transistors without even a Single Error? Where is the error within the whole Design?

3. Outline What is Error Diagnosis? What is Error Diagnosis? Diagnosis Approaches Diagnosis Approaches Simulation Based Diagnosis Simulation Based Diagnosis SAT-based Diagnosis SAT-based Diagnosis Relation Between the Approaches Relation Between the Approaches Comparison of the Approaches Comparison of the Approaches Case Study Case Study Conclusion Conclusion

4. Error Diagnosis is... Locating the source of an error or fault Locating the source of an error or fault If an Error exists, it should be diagnosed and corrected! If an Error exists, it should be diagnosed and corrected! Several Automated Approaches Several Automated Approaches

5. Diagnosis Approaches Manual Error Diagnosis is very time consuming and challenging with increasing complexity of designs Manual Error Diagnosis is very time consuming and challenging with increasing complexity of designs Structural Approaches Structural Approaches Rely on similarities between the specification and the implementation Rely on similarities between the specification and the implementation Fails with optimizations in the synthesis Fails with optimizations in the synthesis Binary Decision Diagram-based Approaches Binary Decision Diagram-based Approaches Defines circuit as graphs Defines circuit as graphs Suffer from space complexity issues Suffer from space complexity issues Test-Vector Based Approaches Test-Vector Based Approaches Simulation based Simulation based Boolean Satisfiability (SAT) based Boolean Satisfiability (SAT) based

6. Basic Definitions Error is Functional mismathes between the specification and the implementationError is Functional mismathes between the specification and the implementation Manual design ErrorManual design Error Complex Circuits + CAD tools ErrorComplex Circuits + CAD tools Error

7. Basic Definitions Test Vector Let the circuit I be a faulty implementation of a specification. A test T is a triple (t,o,v), where t= test vector in terms of primary input values of I and causes erroneous value at the primary output o= erroneous output value at the primary output v= correct output value for primary output t=[1,0,1]; o=1; v=0

8. Basic Definitions Diagnosis problem Let the circuit I be a faulty implementation of a specification and let T be a test-set of m tests. Diagnosis problem is to determine a set of candidate gates C={g 1,..,g c } where a correction can be applied to rectify the tests in T

9. Simulation and SAT based Approaches Use a set of Test Vectors Use a set of Test Vectors Can be applied to both Combinational and Sequential Circuits Can be applied to both Combinational and Sequential Circuits Robust with large designs Robust with large designs

10. Simulation Based Diagnosis Definition: “Controlling Value” A ‘Value’ at an input of a logic function is ‘Controlling’ if the output value of the logic changes when that input value complemented E.g: Both inputs of an XOR gate is controlling value since any change at the inputs complements the output IN 1IN 2OUT 000 011 101 110

11. Simulation Based Diagnosis (2) Path Trace Algorithm Path Trace Algorithm For all vector set: For all vector set: Simulate t to establish values of internal signals Simulate t to establish values of internal signals Mark the gate with the erroneous primary output Mark the gate with the erroneous primary output For each marked gate For each marked gate Mark the inputs with controlling value Mark the inputs with controlling value Mark all inputs if no controlling value Mark all inputs if no controlling value Each marked net is a candidate set Each marked net is a candidate set

12. Simulation Based Diagnosis (3) Interpretation of the diagnosis result depends on the number of errors Interpretation of the diagnosis result depends on the number of errors Single error is diagnosed via the intersection of candidate sets Single error is diagnosed via the intersection of candidate sets For Multiple errors number of errors are considered For Multiple errors number of errors are considered After correcting each error re calculate the test set After correcting each error re calculate the test set There is no guarantee that the decisions are definitely correct There is no guarantee that the decisions are definitely correct Back track ability is required Back track ability is required For basic approach solution is not guaranteed For basic approach solution is not guaranteed

13. SAT-Based Diagnosis SAT instance is generated SAT instance is generated A copy of circuit is created for each test in the SAT instance A copy of circuit is created for each test in the SAT instance Circuit with multiplexers at gates to allow corrections Circuit with multiplexers at gates to allow corrections A correction to the gate output is applied if the select line of the multiplexer is set to 1 A correction to the gate output is applied if the select line of the multiplexer is set to 1

14. SAT-Based Diagnosis (2) BasicSATDiagnose Algorithm: BasicSATDiagnose Algorithm: For each triple of T For each triple of T Create an instance i of I in the SAT-instance Create an instance i of I in the SAT-instance Constrain o to assume the correct value v Constrain o to assume the correct value v Constrain inputs to the values of t Constrain inputs to the values of t Insert Multiplexers at gates that are considered for correction Insert Multiplexers at gates that are considered for correction For i=1 to k For i=1 to k Constrain the number of select-inputs with value 1 to be at most i Constrain the number of select-inputs with value 1 to be at most i Enumerate all solutions and add a blocking clause for each solution Enumerate all solutions and add a blocking clause for each solution

15. SAT-Based Diagnosis (3) SAT solver is used to solve the SAT instance SAT solver is used to solve the SAT instance Select lines of MUXes are the free variables Select lines of MUXes are the free variables Each solution set of free variables is a solution to diagnosis problem Each solution set of free variables is a solution to diagnosis problem Number of error limit is increased iteratively to get the minimum number of corrections Number of error limit is increased iteratively to get the minimum number of corrections This is called Basic SAT approach (BSAT) This is called Basic SAT approach (BSAT)

16. Advanced SAT-Based Diagnosis Applies several heuristics to improve the performance of BSAT Applies several heuristics to improve the performance of BSAT Algorithms to reduce the search space Algorithms to reduce the search space Test sets are split into smaller ones to reduce the size of the SAT instance Test sets are split into smaller ones to reduce the size of the SAT instance Techniques do not change the solution space but reduces the run time Techniques do not change the solution space but reduces the run time

17. Comparison of the Approaches Number of candidate Error Sites: Large in BSIM, k candidates in BSAT Number of candidate Error Sites: Large in BSIM, k candidates in BSAT Ability to return valid corrections: Ability to return valid corrections: BSAT, Advanced BSIM and Advanced BSAT approaches return valid corrections BSAT, Advanced BSIM and Advanced BSAT approaches return valid corrections BSIM does not guarantee to find the valid corrections BSIM does not guarantee to find the valid corrections BSIM guide the designer to locate the error BSIM guide the designer to locate the error

18. Comparison of the Approaches Effect Analysis Effect Analysis Done inherently by the BSAT diagnosis Done inherently by the BSAT diagnosis Advanced Simulation techniques carry out via re-simulation Advanced Simulation techniques carry out via re-simulation Structural Information Structural Information May be used by simulation techniques May be used by simulation techniques Advanced BSAT techniques use to prune the search space Advanced BSAT techniques use to prune the search space

19. Comparison of the Approaches |I|=Size of the Circuit m= number of Tests k= number of Errors Simulation engine is a crucial issue due to large number of tests and complex circuits Simulation engine is a crucial issue due to large number of tests and complex circuits BSIM has a linear time complexity O(|I|*m) BSAT has exponential complexity of O ( 2 |I|*m*2+|I|+l )

20. Comparison of the Approaches Space complexity of BSIM is smallest, Each test can be applied independently Space complexity of BSIM is smallest, Each test can be applied independently O(|I| + m) For BSAT circuit is stored for each test up to depth of k search level For BSAT circuit is stored for each test up to depth of k search level O(k*|I|*m)

21. Runtime of the Basic Approaches *BSAT guarantees a valid correction

22. Quality of Basic Approaches BSAT is slower but returns by far the best results Even simple approaches have good quality and helps the designer

23. CASE STUDY: CASE STUDY: Error Diagnosis in Equivalence Checking of High Performance Microprocessors Equivalence checking of RTL and transistor level models of high performance microprocessors Error Diagnosis via Simulation Based Techniques

24. CASE STUDY Gate level models are used rather than transistor level models in error diagnosis of microprocessors by the previous approaches Due to performance constraints custom logic is used (Self timed components, dynamic logic vs.) Boolean model extraction tools can not be used The model described captures transistor level dynamic behavior Counts bidirectional transistors, charge sharing and different transistor strengths Signal timing and transistor strengths may also cause errors error diagnosis becomes even more challenging

25. CASE STUDY Equivalence Checking is done by Symbolic Trajectory Evaluation (STE) between RTL and transistor level models Formal verifcation technique Combines symbolic simulation with ternary simulation. 0, 1, X values are used 0, 1, X values are used Verification is done via assertions as Verification is done via assertions as “antecedent implies consequent” Generated Automatically from the RTL Model

26. CASE STUDY Counter Examples are generated for assertions that fail Characteristics of Error Diagnosis Small Number of Error Locations Fast Contains Actual Error Locations

27. CASE STUDY PathBacktrace(nd): Input: Comparison node, counter example, implementation Output: Diagnosis nodes in Controlling list If nd is input or is already processed then return Compute excitation function F for nd from transistor level for every node x in support of F if x is controlling then add x to Controlling list L, if not already added end for if L=[ ] then PathBacktrace(y) for all nodes y in support of F else choose a node y in L and PathBacktrace(y)

28. Path Trace Example a b c d out e g f h & + & + ~ a b c d g f h & & + 1 1 1 1 1 10011001 0 0 0 0 10011001 Specification Implementation +

29. a b c d out e g f h & + & + ~ 1 1 1 1 1 10011001 Controlling= [b; g; d; a; e; f; h] [b] e g [g; d] h [a; e] f [f; h] out Controlling Node

30. a b c d out e g f h & + & + ~ 0 0 0 0 0 11011101 Controlling= [b; c; g; e; f; h] [b] e [c] g [g] h [e] f [f; h] out Controlling Node PathBacktrace = [b; e; g; h; f]

31. CASE STUDY Complemention is applied Complemention is applied Scalar forward simulation of design Applied to nodes generated by Path Backtrace Checks if changing the value of the node is observable at the output Reduces the number of error locations Reduces the debugging and verification time

32. Complementation Example a b c d out e g f h & + & + ~ 1 1 1 1 1 Complement out Changed? f =0 no h=0 no g=0 no e=0 yes b=1 yes PathBacktrace = [b; e; g; h; f] Complementation= [b; e] 0 1 0 1 0 0 0 0 1 1 0 0 1

33. CONCLUSION Error Diagnosis is a major step in the design process of Microelectronic Circuits Error Diagnosis is a major step in the design process of Microelectronic Circuits Automated Diagnosis Approaches are used Automated Diagnosis Approaches are used Simulation based approaches are faster and needs less resources but has limited help to the designer Simulation based approaches are faster and needs less resources but has limited help to the designer SAT-Based approaches are slower but guarantees the solution SAT-Based approaches are slower but guarantees the solution An application of Simulation based techniques is presented An application of Simulation based techniques is presented We presented automated techniques to find errors in the circuit designs that will reduce the design cycle We presented automated techniques to find errors in the circuit designs that will reduce the design cycle

34. REFERENCES - On the relation between simulation-based and sat-based diagnosis, G. Roy, S. Safarpour - On the relation between simulation-based and sat-based diagnosis, G. Roy, S. Safarpour - Error Diagnosis in Equivalence Checking of High Performance Microprocessors, Alper Sen - Error Diagnosis in Equivalence Checking of High Performance Microprocessors, Alper Sen - Design Error Diagnosis and Correction via test Vector Simulation, A. Veneris et al. - Design Error Diagnosis and Correction via test Vector Simulation, A. Veneris et al.

35. QUESTIONS?