1. Chapter 4 Combinational Logic

2. 4.1 Introduction   Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of logic gates whose outputsat anytime are determined from only the present combinationof inputs. 2

3. 4.2 Combinational Circuits  Logic circuits for digital system  Sequential circuits    contain memory elements the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs 3

4.  A combinational circuits  2possible combinations of input values n Combinationa l circuits Combinatixnal xoxic Circuit n inputm output variables 4  Specific functions  Adders, subtractors, comparators, decoders, encoders, andmultiplexers

5. 4-3 Analysis Procedure  A combinational circuit    make sure that it is combinational not sequential  No feedback path derive its Boolean functions (truth table) designverification

6. A straight-forward procedure = AB+AC+BCF 2 T 1 = A+B+C 6 1 = AxB+C T T 2 3 1 = ABC = F2'T1 = T3+T2F

7.  F 1322113221 = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C“)(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B‘C+AB‘C'+ABC = T+T=F=F'T+ABC 7

8.  The truth table 8

9. 4-4 Design Procedure The design procedure ofcombinational circuits      State the problem (system spec.) determine the inputs and outputs the inputand output variables are assigned symbols derivethe truth table xerive the simplified Boolxan functionx draw the logic diagram and verify the correctness 9   derive the simplifi edb oolean functions

10.  Functional description    Boolean function HDL (Hardware description language)   Verilog HDL VHDL Schematicentry number of gates number of inputs to a gate Propagation delay number ofinterconnection limitations of the driving capaeilities 10  Logic minimization     

11. Cdde conversion example  BCD to excess-3 code  Thetruth table 11

12. The maps 12

13.  The simplified functions  z = D' y = CD +C'D‘ x = B'C + B‘D+BC'D' w = A+BC+BD  z = D' y = CD +C'D'= CD + (C+D)' x = B'C +B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD 13  Another implementation 

14.  The logic diagram 14

15. 4-5Binary Adder-Subtractor  Half adder     0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ;1+ 1 = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table 15

16.     S = x'y+xy' C = xy the flexibility for implementation S=x  y S = (x+y)(x'+y')  S = (C+x'y')' C = xy = (x'+y')x  16  S‘= xy+x'y'

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18. CS 15118  A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. ◦ For a carry-in (Z) of 0, it is the same as the half-adder: ◦ For a carry- in (Z) of 1: Z0000 X0011 + Y+ 0+ 1+ 0+ 1 C S000 1 1 0 Z1111 X0011 + Y+ 0+ 1+ 0+ 1 C S0 11 0 11

19.  Full-Adder    The arithmetic sum of three inputbits three input bits   x, y: two significant bits z: the carrybit from the previous lower significant bit Two outputbits: C, S 18

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21.   S = x'y'z+x'yz'+ xy'z'+xyz C = xy+ xz + yz S = z  (x  y) = z'(xy'+x‘y)+z(xy'+x'y)' = z‘xy'+z'x'y+z(xy+x‘y') = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy 20

22. Binary adder 21

23.  Carry propagation   when the correct outputs are available the critical path counts (the worst case) 22

24.  Reduce the carry propagation delay    employ faster gates look-ahead carry (more complex mechanism, yet faster) carrypropagate: P iiiiii = A BB carry gxnerate: G= AB 3222221210210032222212102100 23       carry generate: G iiiiii = AB sum: S = P iiiiii CC carry: C i+1iii = G +P C C C 10001000 =G=G+PC 211111000211111000 = G+PC= G+P(G+PC) = G 110100110100 +PG PC C= G+PC= G+PG PG+P+PPPC

25.  Logicdiagram Digitxl Circuits 2x2x

26. 4-bit carry-look ahead adder  propagation delay xigital Cixcuits 25

27. Binary subtractor   A-B = A+(2’s complement of B) 4-bit Adder-subtractor  M=0, A+B; M=1, A+B’+1 26

28.  Overflow     The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow 27 Example: