1. Sharif University of Technology Department of Computer Engineering Digital System Design Verilog ® HDL Basic Concepts Digital System Design Verilog ® HDL Basic Concepts Alireza Ejlali

2. 2 Verilog Syntax White Space White Space Space \b Space \b Tab \t Tab \t Newline \n Newline \n Comments Comments /* Comments */ /* Comments */ // Comments // Comments Number Specification (‘b, ‘h, ‘o, ‘d) Number Specification (‘b, ‘h, ‘o, ‘d) 4’b1111 4’b1111 12’habc 12’habc 16’d255 16’d255 Default length = at least 32, Default radix = decimal Default length = at least 32, Default radix = decimal

3. 3 4-Value Logic Set of values = {0,1,x,z} Set of values = {0,1,x,z} 12’h13x, 4’b1x0z 12’h13x, 4’b1x0z Z=? Z=? Extension Extension Filled with x if the specified MSB is x Filled with x if the specified MSB is x Filled with z if the specified MSB is z Filled with z if the specified MSB is z Zero-extended otherwise Zero-extended otherwise 6’hx, 32’bz, ‘hf0 6’hx, 32’bz, ‘hf0 Two’s complement Two’s complement -6’d3 = 6’d61 (- 000011=111101) -6’d3 = 6’d61 (- 000011=111101) -6’b01zz00 = 6’bxxxxxx -6’b01zz00 = 6’bxxxxxx Readability Readability 16’b0110_1011_0100_0001 16’b0110_1011_0100_0001

4. 4 Value Set Value level HW Condition 0 Logic zero, false 1 Logic one, true xUnknown z High imp., floating Strength level TypesupplyDriving strongDriving pullDriving largeStorage weakDriving mediumStorage smallStorage highz High Impedance

5. 5 Signal Strength Driving Driving Storage Storage

6. 6 wire and reg wire wire Used to represent connections between HW elements Used to represent connections between HW elements Default Value = z Default Value = z reg reg Retain value until next assignment Retain value until next assignment NOTE: this is not a hardware register or flipflop NOTE: this is not a hardware register or flipflop Default Value = x Default Value = x

7. 7 Vectors Syntax: Syntax: wire/reg [msb_index : lsb_index] data_id; wire/reg [msb_index : lsb_index] data_id; Example Example wire a; wire [7:0] bus; wire [31:0] busA, busB, busC; reg clock; reg [0:40] virtual_addr; Access to parts of a vector Access to parts of a vectorBus[2:0]

8. 8 Other data types Integer, Real, Time,… Integer, Real, Time,…