1. Si Strip FEE Vince Cianciolo VTX Group Meeting 01 June 2004

2. Outline Overview of strip FEE ROC details “ORNL testboard” Current development efforts Concerns

3. Strip FEE Overview 1) Signal Conditioning 2) L1 Latency 3) Accepted event buffer - This talk Get signals on/off detector Fiber? LVDS? - John’s talk Relatively straightforward - Analog pipeline control internal to SVX4 Basics exercised w/ “ORNL Testboard” – this talk Final version needs input from DCM design – Chi’s talk

4. CDF Hybrid Starting point for thinking about the ROC is the CDF equivalent (hybrid) –4 conductor-layer PC board handling 4 daisy- chained SVX4s –Bonded to a BeO substrate to handle thermal requirements 40 mm 28 mm Signal inputs wire-bonded to sensors.

5. A PHENIX Version In 10% more area we have nearly twice as many chips. Unlike CDF our ROCs cover the entire sensor, they aren’t simply connected to an edge. –Direct consequence of channel density. We take advantage of this by incorporating the bus directly into the ROC. –Actually, the bus is already there (signals and power), so this saves a significant amount in our material budget. –The tricky part is making the connections. We are starting to explore a few ideas, but don’t believe this will be a serious issue.

6. SVX4 Details Digital I/O Developed by FNAL/Berkeley ~5000 chips available –FNAL can test 128 8-bit channels/chip Compatible w/ PHENIX DAQ –5-event  4-event buffering ~675 + 45  C e rms noise Double correlated sampling, dynamic pedestal subtraction to mitigate common mode noise On-board 0-suppression available.

7. SVX4 Constraints on Barrel Design 6 SVX4 chips per ROC 2 ROCs per sensor 4 or 5 sensors per stave –Depends on z-extent ~2  (R 1 +R 2 )/3 = 2(R 1 +R 2 ) staves required for two layers Assumptions: –5000 SVX4 available, yield ~ 97% –Characterized by CDF hybrid production: 64% perfect 25% “fair” (some broken pipeline caps <1 broken channel) 8% 1 bad channel 3% bad –Hybrid yield 87% (observed for CDF hybrids) –Want 15% spare hybrids Limit design to 3650 SVX4s, 608 ROCs, 304 sensors –4 sensors/stave  R1+R2 maximum = 38 cm –5 sensors/stave  R1+R2 maximum = 30 cm

8. RCC Details State machine w/two event buffering –Required to meet PHENIX bandwidth requirements –Reduces consequences of single-point failures Will be developed as an FPGA Can be implemented as an ASIC if required –Radiation environment –Known-good bare die.

9. Bandwidth Considerations SVX4 buffers analog data, not digitized data. To satisfy PHENIX requirements we must digitize and readout the chips (into the RCCs) in T conv <40  s: –256/M + 6*(1+128*occupancy)/N < 375 clocks M is digitization clock N is readout clock 6 is the # of SVX4s per RCC –w/ M=N=1 maximum occupancy is 14% Given 2 nd pixel layer, perhaps we can go to 12 SVX4s per ROC We must also readout entire ladder in T readout <40  s: –48 [or 60] *(1+128*occupancy)/X < 375 clocks X is readout clock –Even if X = 4, maximum occupancy is 28%  0-suppression required.

10. “ORNL Testboard” Testboard controlled by LabView-based GUI. –Allows us to specify and download: Serial control files (mimics ARCNet), and Mode-bit control strings (mimics the GTM) to the SVX4’s on a CDF hybrid through the input FIFO. –Mode-bit strings can contain L1 accepts and ENDDAT signals which will cause the SVX4 to dump data into the output FIFO buffer (mimics DCM) where they can be read by the PC. Allowed us to understand SVX4 control & configuration. Showed SVX4 compatible w/ PHENIX DAQ. Provided (unintentionally) a DAQ interface for sensor/SVX4 testing. Clock Output FIFOInput FIFO FPGA SVX4 CDF Hybrid Wire bonding CDF Hybrid Testboard Ribbon Cable PC LabView GUI USB Connection

11. SVX4 Control Timing Diagram

12. ROC Functional Equivalent Modified Testboard Current Development Effort

13. SVX4-A SVX4-B SVX4-C Hybrid Board A2 SVX4-A SVX4-B SVX4-C Hybrid Board B2 SVX4-A SVX4-B SVX4-C Hybrid Board B1 SVX4-A SVX4-B SVX4-C Hybrid Board A1 RCC NIM-resident Connectors daisy-chain on front-panel One ROC-equivalent One Board in Three RCC Board A RCC Board B

14. ROC Functional Equivalent Allows us to test complete circuit w/ a reasonable-sized form factor. Will allow a multiple-sensor test early next year.

15. ROC Functional Equivalent Modified Testboard Current Development Effort

16. Modified Testboard Add LVL1 input Correct “blue wires” Change form factor (NIM) Update firmware: Handle multi-event buffering Handle daisy-chained ROCs Will allow complete stave testing w/o completed DCM. Will be the basis of production ROC testing.

17. Status Circuit diagrams being finalized for all boards. –Expect to submit board fab orders this month. Layout for hybrid board will largely follow CDF example (low-risk). –Need some iteration w/ Junji et al., on how to best incorporate pitch adapter. Layout for RCC board “trivial”. –Make sure FPGA control handled correctly. Testboard circuit mods also trivial. –Firmware mods to follow.

18. Concerns Signal-to-noise AC vs DC coupling Sensor orientation Thickness

19. Signal to Noise Bad previously –10:1 for 400  m sensors w/ VA2 Common mode? –Check w/ correlated noise plot –If not, expect worsening by  (1000/80) for VA2  SVX4 due to integration time. “Idealized” performance estimated (Junji) for 500  m sensors w/ SVX4: 14:1. –This would be fine for realized performance. –Junji measuring performance w/ SVX4 (CDF hybrid).

20. Signal-to-noise AC vs DC coupling Sensor orientation Thickness Concerns

21. AC vs. DC Coupling Sensors DC coupled, SVX4 expects AC coupling. At room temperature a “typical” sensor dark current is 10 nA. –Needs to be measured for a larger sample of sensors. Dark current expected to get significantly worse (~x10) as sensors are exposed to radiation. This current causes a number of problems: –Saturation of input amp. –Additional noise. –Baseline shift.

22. Current Effects Saturation of input amplifiers –At 10 nA the amps (200 fC dynamic range) saturate in 20  s. Can reset once per abort gap (12  s). –OK, although there could be a problem depending on how typical 10 nA is. There is little room for radiation-induced current increases. Additional noise –10 nA gives ~6000 electrons injected in a 106 ns cycle. –Jitter (  6000 ~ 80) gives additional (15%) noise source. Obviously this is also a much larger problem as currents increase due to aging. Baseline shift –The current is very temperature sensitive At T room  T=5 o changes current by ~ x2. –Such a change would represent a massive pedestal shift (more than 1/3 rd of the expected signal size).

23. AC/DC Mitigation Strategies Cooling the sensors (5 o C) or AC coupling them makes all these problems disappear. AC coupling –We cannot AC couple the sensors directly. –Instead add an RC chip between sensors and SVX4. –Problems: Precious real estate. Adds two extra fine-pitch wire bonds for each channel. Cool sensors. –Veljko strongly recommended this. –Dave L. will need to comment on the difficulties.

24. Signal-to-noise AC vs DC coupling Sensor orientation Thickness Concerns

25. Present Scheme Sensor has x and u readout. Bond pads at indicated locations. Connections between sensor and chips will make it impossible to incorporate bus into ROC. –Complicates connections. –Adds another piece to develop. –Adds significant material. Readout bus

26. Reorient Traces Solution: bring traces out the long side of the sensor. Picture shows how to do this w/ extra metallization layer. Junji figured had a better idea that doesn’t require extra layer. Zheng Li felt this would be a cosmetic change: –Doesn’t change underlying sensor, only readout metallization. –Modest capacitance increase. –But, it is still a change and needs to be tested. Added bonus: eliminates 700 um dead space between sensors (2.5%)

27. Signal-to-noise AC vs DC coupling Sensor orientation Thickness Concerns

28. Components Sensor – 0.53% X 0 –Silicon only –Bias plane? Metallization layer? Add 0.1% X 0 ? Cooling – 0.7% X 0 –CDF required 0.6% X 0 and had only 10% the power density. ROC???

29. CDF Experience We have a higher chip density (+0.05% X 0 ). The substrate is as thin as it can be. We likely need to have 4 more dielectric layers (higher trace density precludes combining power/trace layers) (+0.12% X 0 ). –Note: this technique requires more dielectric layers than one would naively expect (doubled) in order to prevent substrate warpage. We may need thicker ground/power layers due to current requirements. We will have more trace conductor. –These can’t be copper. –These can be silver (Au flash on top for corrosion resistance). –Call it even in terms of X 0 for now. ComponentMaterialX0LengthWidthHeightQty%X0 SVX4Silicon93.69.116.40.340.098 Capacitors, resistors, epoxy, wire-bond encapsulation0.108 SubstrateBeO14420380.38110.265 Dielectricglass10020380.03870.266 Ground/Power PlanesAu3.3520380.0037630.337 Trace PlanesAu3.3520380.00056420.034 Total 1.108 W/this technique we’re looking at ~1.3% X 0 for the ROC alone.

30. ATLAS Strips Use a Cu/polyimide hybrid w/ a carbon substrate. They have a power density comparable to PHENIX. The hybrid material itself (substrate, conductor, dielectric) totals 0.51% X 0. –Compare to 1% X 0 for CDF equivalent. Adding chips (.14%), miscellaneous (.15%) and one extra conductor layer (.08%), this technique might reduce the ROC thickness to 0.88% X 0. Added bonus: general consensus is that Cu/polyimide is much cheaper.

31. Cu/Polyimide vs. BeO Apparent advantages to using a Cu/polyimide hybrid construction. –Cheaper –Thinner Additional investigation is needed. –Thermal properties. –Reliability. –Yield. Still estimate ~2.2% X 0 per layer.