1. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re1 Valerio Re INFN Pavia and University of Bergamo on behalf of the SuperB collaboration The Vertex Detector at the Factory Vertical Integration Workshop Schloss Ringberg, April 6-9, 2008

2. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 2V. Re Outline The SuperB Project Vertex Detector Design Issues Viable options for Layer0: –Striplets, CMOS Monolithic Active Pixels, Hybrid Pixels Status of the R&D on Layer0 options Conclusions & Perspectives

3. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 3V. Re Introduction Flavour physics is rich, promises sensitivity to New Physics –Physics case established and clear,... but large statistics (50-100 ab -1 ) is needed Present B-Factories (PEP-II and KEKB) integrated 1.2 ab -1, exceeding their design goals, with peak Luminosity ~1.2-1.7 x10 34 cm -2 s -1...but an upgrade of 1-2 orders of magnitude in Luminosity is needed to get 50ab -1 Increasing Luminosity by raising the current of PEP-II/KEKB is expensive and difficult –wall plug power and detector background explosion –effective limitation around 5x10 35 cm -2 s -1 Alternative approach for a SuperB design, exploiting ILC R&D, presented for the first time at Hawaii workshop in March 2005. After several optimizations we have a SuperB design based on 4 and 7 GeV rings (similar to test damping rings for ILC) with moderate currents (~2A) and final focus (ILC-like)  L=10 36 cm -2 s -1 –This approach allows to (re-) use existing detectors and machine components.

4. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re4 The SuperB Process International SuperB Study Group on –Physics case, Machine, Detector International steering committee established, chaired by M. Giorgi. Members from –Canada, France, Germany, Italy, Russia, Spain, UK, US –Close collaboration with Japan, although not formalized Regular workshops –Five workshops held at SLAC, Paris, Frascati –SuperB Meeting at Daresbury –Two Accelerator retreats at SLAC Conceptual Design Report –Published in March 2007 –Describes Physics case, Accelerator, Detector, including costs International Review Committee appointed by INFN to review CDR –Preliminary report by end of 2007 –Final report in Spring 2008 More information: www.pi.infn.it/SuperB

5. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re5 SuperB Detector Babar and Belle designs have proven to be very effective for B-Factory physics  Follow the same ideas for SuperB detector  Try to reuse same components as much as possible Main issues:  Machine backgrounds – somewhat larger than in Babar/Belle affects mainly SVT layer 0 design  Beam energy asymmetry – a bit smaller smaller bean pipe and improved SVT resolution needed to preserve vertex z reconstruction performance  Strong interaction with machine design More details in:  http://www-conf.slac.stanford.edu/superB2008/default.asp - SLAC Detector R&D Workshop (Feb. 14 – 16, 2008) http://www-conf.slac.stanford.edu/superB2008/default.asp  https://agenda.infn.it/conferenceDisplay.py?confId=163 – Review (Nov 12-13, 2007) https://agenda.infn.it/conferenceDisplay.py?confId=163

6. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re6 SuperB detector feasible with technologies available today Baseline is reusing large (expensive) parts of Babar (or Belle)  Quartz bars of the DIRC  Barrel EMC CsI(Tl) crystal and mechanical structure  Superconducting coil and flux return yoke. Some areas require moderate R&D and engineering developments to improve performance  Small beam pipe technology  Thin silicon pixel detector for first layer  Drift chamber CF mechanical structure, gas and cell size  Photon detection for DIRC quartz bars  Forward PID system (TOF or focusing RICH)  Forward calorimeter crystals (LSO)  Minos-style scintillator for Instrumented flux return  Electronics and trigger – need to revise Bfactory “½-track” trigger style  Computing – large data amount

7. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 7V. Re SuperB Vertex Detector Design Issues Smaller beam energy asymmetry 7+4 GeV   =0.28 SuperB (  =0.55 BaBar) Reduces average vertex separation by ~ 2 w.r.t. BaBar: ~130  m @ SuperB Radius of beam pipe and first SVT layer need to be reduced : Vertex resolution dominated by first layers: the closer to the IP the better Most benchmark analyses require excellent vertex resolution: Background fighting in rare decays benefits from improved vertex resolution SuperB SVT concept based on Babar SVT with modifications required to operate at a L=10 36 cm -2 s -1 and with the reduced SuperB boost Main Issues Impact on > Detector segmentation to reduce occupancy to acceptable level (<10%) > Radiation hardness Dose ~ 6 Mrad/yr Equivalent fluence ~ 6x10 12 n/cm2/yr Machine backgrounds with high luminosity/ “squeezed” bunches/low currents: Present estimate (simulation) of total background rate at SVT inner layer location ~ 5 MHz/cm2 Vertex Separation significance BaBar Improves SuperB boost x5 safety

8. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re8 SuperB SVT Geometry Baseline: use an SVT similar to the BaBar one adding a Layer0 Cannot reuse BaBar SVT because of radiation damage Fast Simulation indicates target performance achievable with: –b.p. inner radius: 1.0cm, –Layer0 radius: 1.5 cm –b.p.+Layer0 material: <0.5%-0.5% X 0 40 cm 30 cm 20 cm Layer0  t resolution (   z) BaBar Improves A beam pipe with r ~ 1 cm highly desirable, but needs to be cooled. Study is in progress to keep total thickness low ~ 0.5 % of X 0 Layer Radius 0 1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 511.4 to 14.6 cm Layer Radius 0 1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 511.4 to 14.6 cm

9. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re9 Layer 0 Options Striplets option: mature technology, not so robust against background. Marginal with background rate higher than ~ 5 MHz/cm 2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2) CMOS MAPS option new & challenging technology: can provide the required thickness existing devices are too slow Extensive R&D ongoing (SLIM5-Collaboration) on 3-well devices 50x50um 2 Hybrid Pixel Option: tends to be too thick. An example: Alice hybrid pixel module ~ 1% X 0 Possible material reduction with the latest technology improvements Viable option, although marginal The BaBar SVT technology is adequate for R > 3cm: use design similar to BaBar SVT Layer0 is subject to large background and needs to be extremely thin: > 5 MHz/cm 2, < 0.5%X 0

10. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 10V. Re Basic R&D for Layer0 (CMOS MAPS and thin strips) started in 2004 within the SLIM5 Collaboration. –Several Italian Institutions involved in the project: BO, PI (coordination), PV-BG, TO, TN, TS. –R&D project supported by the INFN and the Italian Ministry for Education, University and Research. SLIM5- Silicon detectors with Low Interactions with Material Realize a demonstration thin silicon tracker with LVL1 trigger capabilities: CMOS monolithic active pixels Thin strip detectors on high resistivity silicon Associative memory system for track trigger Low mass mechanical support and services Test beam foreseen in 2008 to measure rate capability, efficiency,resolution SLIM5 Purpose: develop technology for thin silicon tracker systems (sensor/ readout/ support structure/ cooling) crucial to reduce multiple scattering effects for future collider experiments (SuperB, ILC) SLIM5 Project

11. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re11 Charge-to-Voltage conversion done by the charge preamplifier The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance), reducing charge loss to competitive N-wells where PMOSFETs are located Fill factor = DNW/total n-well area ~90% in the prototype test structures PREAMPL SHAPER DISCLATCH Classical optimum signal processing chain for capacitive detector can be implemented at pixel level: Deep N-Well (DNW) sensor concept New approach in CMOS MAPS design compatible with data sparsification architecture to improve the readout speed potential

12. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re12 DNW MAPS 130 nm STM process IC group contribution: Pavia (PV)-Bergamo(BG) analog front-end Pisa(PI)-PV-BG in pixel digital logic Bologna-PI digital readout architecture APSEL1 Sub. 12/2004Sub. 8/2005 Sub. 8/2006 APSEL2_90 Sub. 9/2006 TEST_STRUCT ST 130 Process characterization APSEL0 Preamplifier characteriz. Improved F-E 8x8 Matrix APSEL2M Cure thr disp. and induction APSEL2T Accessible pixel Study pix resp. ST 90nm characterization Sub. 11/2006 APSEL2D Sub. 7/2007 APSEL3D APSEL3_T1, T2 Test digital RO architecture 8x32 matrix. Shielded pixel Data Driven sparsified readout Test chips to optimize pixel and FE layout APSEL2_CT Test chips for shield, xtalk Sub. 5/2007Sub. 7/2007 APSEL4D Sub. 11/2007 32x128 matrix. Data Driven sparsified readout Beam test Sep. 2008 SLIM5

13. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re 13 Fast Readout Architecture for MAPS Data-driven readout architecture with sparsification and timestamp information under development. In the active sensor area we need to minimize: –the logical blocks with PMOS to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor. –digital lines for point to point connections to allow scalability of the architecture with matrix dimensions and to reduce cross talk with the sensor underneath. Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: –Register hit MP & store timestamp –Enable MP readout –Receive, sparsify, format data to output bus Data lines in common 2 MP private lines MP 4x4 pixels Periphery readout logic Column enable lines in common Data out bus APSEL3D: 256 pixels under test APSEL4D: 4k pixels under test 50x50 um pitch

14. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re14 From APSEL2 to APSEL3 Cross talk between digital lines and substrate –Requires aF level parasitic extraction to be modeled Relatively small S/N ratio (about 15) –Especially important if pixel eff. not 100% Power dissipation 60  W/pixel –Creates significant system issues M1 M2 M3 M5 M6 M4 Analog routing (local) Digital routing (local/global) Shield ( VDD/GND ) APSEL3 Redesigned front-end/sensor APSEL3D Digital lines shielding Optimize FE Noise/Power: Reduce sensor capacitance (from 500 fF to ~300 fF) keeping the same collecting electrode area –reduce DNW sensor/analog FE area (DNW large C) –Add standard NWELL area (lower C) to collecting electrode. New design of the analog part Optimize sensor geometry for charge collection efficiency using fast simulation developed: –Locate low efficiency region inside pixel cell –Add ad hoc “satellite” collecting electrodes APSEL3 Power=30  W/pixel: Perfomance APSEL2 issues APSEL3 expected performance FE VersionGeom. ENC (PLS)  (@5   S/N APSEL2 data A50 e-88.7%14 APSEL3 Transc. ABAB 41 e- 93.6% 99.4% 16 18 APSEL3 Curr. Mirror ABAB 31 e- 98.6% 99.9% 22 24

15. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re15 APSEL3D 256 pixel matrix with sparsified readout and timestamp - submitted 7/2007 Innovative mixed mode design –Pixel cell with full custom design and layout –Sparsifying logic synthetized in std-cell from VHDL model Essential for large matrix design with complex logic Encouraging results on hit efficiency from VHDL simulation: –  > 99% with hit rate up to several hundreds MHz/cm 2 (small matrix/preliminary study) 256 pixels - 50  m pixel pitch

16. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re16 An example of sensor optimization DNW collecting electrode Competitive Nwells 3x3 MATRIX old sensor geom Satellite nwells connected to central DNW elect 3x3 MATRIX sensor optimized With old sensor geometry (left) Efficiency ~ 93.5% from simulation (pixel threshold @ 250 e- = 5xNoise) Inefficient regions shown with dots (pixel signal < 250 e-) Cell optimized with satellite nwells (right) Efficiency ~ 99.5%

17. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re17 APSEL3T1 pixel cell DNW + NMOS Analog section PMOS Analog section Digital section Nwell satellite collecting electrodes 50  m Sensor geometry B Sensor geometry A 50  m

18. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re 18 APSEL3 chips now under test 90 Sr electrons Landau mV S/N=20 Cluster signal (mV) Noise events properly normalized Very preliminary! S/N = 20 for MIP from Sr90 Absolute calibration of noise and gain still under way APSEL3T1 Preliminary First test on APSEL3D (256 pixels): readout works as expected…with some bugs found! Noise scan (hit rate vs discriminator threshold) to measure noise and threshold dispersion.  Metal shield effective to reduce crosstalk effects due to digital lines crossing the pixel. This source is now at the level of the pixel noise…  But some digital crosstalk still present in the APSEL3 series…different source? Power distribution problem? Vth (DAC) APSEL3D Preliminary Occupancy

19. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re19 APSEL4D : just received from foundry 4096-MAPS matrix 100k std-cell area STM 130nm Area 7053  m  3034  m Architecture is data-driven, there is an on-line sparsification The hits are on-line associated with a 8-bit Time-Stamp The pixels, the MCs, the MRs and the MPs are numbered to define the 21-bit formatted output data - 128 columns  32 rows, - 32 MacroColumns (MC)  8 MacroRows (MR), - 256 MacroPixels composed of 4  4 pixels APSEL4D noise scan (last week)

20. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re 20 Mechanics & Module design R&D FEA for MAPS module proposed indicates power removal possible with a support/cooling thickness ~ 0.3% X0: –Extensive R&D activity on microcooling –Need to demonstrate feasibility with meas. on mechanical prototype –Thermohydraulic Testbench in prep. for accurate thermal measurements Mechanical activity also to optimize the design of the striplets option. MAPS module proposed (AlN support + minichannel with cold liquid) Two MAPS layers (up/down) placed on the mechanical support forming a ladder. Each chip: 12.8mm x 12.8mm. Total Layer0 thickness: 0.5 % X0 0.1 % (Si) + 0.3 % (Supp+Cooling) + 0.1 % (bus/Cu) MAPS power dissipation is large (in the active area!) –Power = 50 μW/cell = 2 W/cm 2 –Power dissipation drives the mechanical problem

21. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re 21 Layer0 striplets R&D issues Technology for Layer0 striplets design well estabilshed –Double sided Si strip detector 200  m thick –Existent readout chip (FSSR2 - BteV) meets the requirements for striplets readout with good S/N ~ 25. –Readout speed and efficiency not an issue with the expected background rate (safety factor x5 included)  6% occupancy in 132 ns time window. –Total thickness 0.45% X 0 = (0.2 % (Si) + 0.1 % (Support) + 0.15 % Multiflex) –Possible reduction in material (  0.35% X 0 ) with R&D on interconnections between Si sensor and FEE: Interconnections critical: high number of readout chans/module (~3000). –Multiple layers of Upilex with Cu/gold traces with microbonding (as in SVT) –Kapton/Al microcables with Tape Automated Bonding (as in ALICE experiment) Conceptual design module “flat” Readout Right Readout Left z HDI Si detector 12.9x97.0 mm 2 1 st fanout, 2 nd fanout HDI

22. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re 22 Module Layer0 (striplets): 3D-view Hybrids Striplets Si detector (fanout cut-away) Upilex fanout Carbon-Kevlar ribs End piece chip Buttons (coupling HDI to flanges)

23. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re23 2008 SVT Test Beam at CERN

24. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re24

25. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re25 Benefits of Vertical Integration Time to explore new pixel technology for SVT Layer0? Can use MAPS readout electronics on a thin chip connected to high resistivity thin pixel sensor? –Improve S/N w.r.t. to CMOS MAPS: pixels on high resistivity substrate are fully depleted Signal proportional to sensor thickness Noise reduced with the lower detector capacitance –Reduce power dissipation (trade off with noise reduction) –Sensor can be extremely radiation hard Can use CMOS MAPS on 2 tiers? (sensor&analog + digital) See talk on 3D activities in Italian HEP labs tomorrow

26. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re26 Perspectives There is a growing international interest and participation to the SuperB Project. The Conceptual Design Report is now under review: –Report by Spring 2008. Next SuperB steps: from CDR to TDR (~ 2 years → 2010): –Accelerator studies continue to optimize the machine parameters. Test in Da  ne began Nov ’07 (crab waist and basic concepts of SuperB IP scheme): so far so good –Detector R&D coordination has been formed (meets every other week) –Physics groups active to update on Physics case (looking at complementarity with LHC). Design and construction: ~ 4 years → 2014 (shorter timescale with respect to ILC and SLHC projects) SuperB could be considered as a “precursor” for next generation experiments (machine & detector)

27. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re27 Backup

28. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re28 Pixel gain calibration Gain measured with a calibration capacitor and the Fe55 calibration peak (15% difference observed) 5.9 keV line (1640 e-) with charge totally collected by a single pixel PWELLNWELL P - EPI-LAYER P ++ SUBSTRATE PWELL INCIDENT PHOTONS Charge entirely collected DEPLETION REGION Charge only partially collected by single pixel Gain=577 mV/fC Gain=490 mV/fC Charge injected on calibration capacitor Fe55 Calibration Peak

29. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re29 MAPS Radiation Hardness Expected Background @ Layer0: –Dose = 6Mrad/yr –Equivalent fluence = 6x10 12 n eq /cm 2 /yr CMOS readout electronics (deep submicron) rad hard MAPS sensor - Radiation damage affects S/N Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping)  fluences  10 12 n eq /cm 2 affordable, 10 13 n eq /cm 2 possible Ionizing radiation: noise increase, due to higher diode leakage current (surface damage)  OK up to 20 Mrad with low integration time (10  s) or T operation < 0 o C, or modified pixel design to improve it Irradiation test performed on several MAPS prototypes, with standard nwell sensor, indicate application for SuperB is viable. APSEL chips irradiation started this summer …. Results from standard nwell MAPS prototypes

30. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re30 Pixel Cell optimization: Signal Developed a fast simulation of the device (ionization and diffusion) to optimize the sensor geometry - APSEL2 data + Fast Simulation 90 Sr electrons –Detailed device simulation (ISE- TCAD) gives similar results –Fair agreement among data and Fast Simulation –Need further tuning of the sensible parameters Fast Simulation identifies low efficiency regions inside pixel –Improve efficiency adding in these areas small satellite nwells connected to the main DNW electrode (low contribution to the total sensor capacitance) –Satellite nwells in the surroundings of the competitive nwell very effective to increase the efficiency

31. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re31 The cure for the crosstalk (APSEL2_CT) Dedicated test structures for crosstalk study on sensor with/without metal shield just received. First tests indicate shield is effective! Induced signal by digital transition (1.2V) reduced in pixel with the metal shield w.r.t no shielded version. Residual crosstalk in shielded pixels below the level of the pixel noise (50 e- ~ 5mV) Still to investigate origin of the positive lobe…though seems not related to the digital signal on the line crossing the pixel no shield with shield sensor shield No shield Digital lines Logic to connect digital signal to lines crossing the pixel 10 mV/div 1 us/div

32. Vertical Integration Workshop, Schloss Ringberg, April 6 –9, 2008 V. Re32 APSEL4D 2 macro-rows 8-bit x 256 MP 32 words 21 bits Matrix Area = 0.1 cm 2