1. BITS Pilani Pilani Campus Pawan Sharma 08-01-2013 ES C263 Microprocessor Programming and Interfacing

2. BITS Pilani, Pilani Campus  Course Overview  Microprocessor based systems  Evolution of microprocessors  Moore’s law Last Lecture

3. BITS Pilani, Pilani Campus  Instruction Set Architecture  Design Example Today’s Lecture

4. BITS Pilani, Pilani Campus The Personal Computer Processor (8086 through Pentium System bus (data, address & control signals) System ROM Interrupt logic (8259) Keyboard logic (8255)DMA Controller (8237) Timer logic (8253) Coprocessor (8087 trough 80387 640KB DRAM Expansion logic Keyboard Speaker Extension slots Video card Disk controller Serial port...

5. BITS Pilani, Pilani Campus  A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome (device that produces regular, metrical ticks (beats, clicks) to coordinate actions of circuits.  The clock rate or frequency of a CPU is determined by the frequency of the clock signal generated from an oscillator crystal. Clock

6. BITS Pilani, Pilani Campus  An instruction set architecture is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and execution and exception handling and external I/O.  ISA refers to the actual set of programmer visible instruction set.  Serves as a boundary between the hardware and software. Instruction Set Architecture (ISA)‏

7. BITS Pilani, Pilani Campus Class of ISA: nearly all ISAs are general purpose register architectures, where operands are either memory or register locations. Register memory (8086): can access memory as part of many instructions Load-store(ARM, MIPS): can access memory with only load and store instructions Memory Addressing: Byte addressing to access memory locations— aligned or un-aligned. Addressing Modes: specify the address of register, constant operands and memory objects-- register, immediate, displacement. Types and sizes of operands: supports operand sizes of 8 bit, 16 bit, 32 bit. Operations: data transfer, arithmetic, logic, control. Control flow instructions: support conditional branches, unconditional jumps, procedure calls and returns. Encoding an ISA: fixed length or variable length. Seven dimensions of ISA

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9. Microprocessor -Fetches Instruction -Executes Instruction

10. BITS Pilani, Pilani Campus Computer Hardware Organization Control unit Arithmetic logic unit Registers common bus memory program storage data storage output unit input unit

11. BITS Pilani, Pilani Campus CPU Data Bus Control signals Add Bus

12. BITS Pilani, Pilani Campus Memory Add Bus Data Bus Read Write Memory – Registers to hold bits

13. BITS Pilani, Pilani Campus 4 bits Ex : 8 Registers Add lines : 3 (Unidirectional)‏ Data lines : 4 (Bidirectional)‏

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15. RAM

16. BITS Pilani, Pilani Campus Design Example

17. BITS Pilani, Pilani Campus User enters desired pH (0-14) and controller gain Reactor tank is provided with three pH sensors, to compute the average pH. Reactor tank has three inputs. (acid flow, base flow effluent discharged from factory  controlled by valves) Design a microprocessor based system to control pH of a solution in a reactor tank. Motorised valve

18. BITS Pilani, Pilani Campus Valve Control - Controlled by stepper motors - 1 step is by 1.8 degrees rotation Valve opening = k P * error Where error = desired pH – measured pH. Error positive- close fully acid valve and open base valve accordingly Error negative- close fully base valve and open acid valve accordingly. 0 – 360 degrees correspond to 0 to 200 steps.

19. BITS Pilani, Pilani Campus Stepper Motor sequence: A B C D 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 CW ACW Use a 4- bit port + driver (nearly 1 A current)

20. BITS Pilani, Pilani Campus pH sensor 0 7 14 Vout pH Voltage output 60mV/pH -420mV - +420mV

21. BITS Pilani, Pilani Campus Interfacing Analog to Digital Converter D0 D7 I0 I7 Start EOC 8-bit ADC ADC 0809 ABCABC ALE OE

22. BITS Pilani, Pilani Campus Input Keys - Numeric keys 0 – 9 - Function keys pH, k P, enter Matrix Keypad interfacing!! - 2 four bit ports.

23. BITS Pilani, Pilani Campus  Two digit Display  Two seven segment display devices to display pH  Memory Interfacing  ROM (4KB) - FF000H – FFFFFH - SRAM (4K) - 00000H – 00FFFH Display Device and storage

24. BITS Pilani, Pilani Campus CPU MemoryI/O Interface Parallel I/O Serial I/O Data Address Control System Block Diagram

25. BITS Pilani, Pilani Campus Method of Approach  Identify input and output devices  Memory requirements  Suitable memory and I/O interfacing  Assembly Language Programming  Assumptions made