1. PASTA 2010 CPU, Disk in 2010 and beyond m. michelotto

2. Production processes m. michelotto

3. 22 nm already in lab

4. After 22nm At 22 nm gate thicknet = 10 Si Atoms After 22/16 nm ? – Change transistor shape – Use III and V group elements Ga, In, P, As, Sb – 3D transistor, secondary gates After 2015 – 11nm: EUV at 13nm (now 193 nm + liquid immersion) – Optical interconnections? Nanotube ? m. michelotto

5. Tick Tock m. michelotto

6. Westmere DP 16 March 2010 first release of Xeon DP on Westmere 32nm m. michelotto modelCores/threadsL3 cacheClock with Turbo Mode OffTDP X5680 6/12 12 MB3.33 GHz130 W X5670 6/12 12 MB2.93 GHz95 W X5660 6/12 12 MB2.80 GHz95 W X5650 6/12 12 MB2.66 GHz95 W L5640 6/12 12 MB2.26 GHz60 W X5677 4/8 12 MB3.46 GHz130 W X5667 4/8 12 MB3.06 GHz95 W E5640 4/8 12 MB2.66 GHz80 W E5630 4/8 12 MB2.53 GHz80 W E5620 4/8 12 MB2.40 GHz80 W L5630 4/8 12 MB2.26 GHz40 W

7. Sandy Bridge DP in Q2 2011 2.8 to 3.4 GHz with Turbo boost disabled 3.0 to 3.8 GHz with Turbo boost enabled 8 DP FP/clock with SSE (128/256 GFLOPS/proc) 256 KB L2 cache/core (9 clocks) 15/20 MB shared L3 cache (25 clocks) Integrated mem controller with max 25.6 GB/s supports DDR3-1600 RAM 8 cores/16 thread or 6 cores/12 threads Default TDP 85 W m. michelotto

8. Ivy Bridge 22 nm shrink of Sandy Bridge (like Westmere is a shrink of Nehalem) About one year after Sandy Bridge m. michelotto

9. AMD from 2009 Series 2000 for 2 socket server 45 nm – 4 core  Shanghai – 6 core  Instanbul Series 8000 for 4/8 socket server 45nm m. michelotto

10. AMD 2010/2011 1 or 2 socket C32 – 4000 series – San Marino platform, 2xDDR3 channel – Optimized for cost and high energy efficiency – Lisbon 4 – 6 cores 45nm – Valencia 6 – 8 cores 32 nm 2 or 4 socket G34 – 6000 series – Maranello platform, 4xDDR3 channel – Optimized for performance per watt and expandibility – Magny Cours 8 -12 cores 45 nm – Interlagos 12 – 16 cores 32 nm m. michelotto

11. Lisbon Q1 2010 4 – 6 cores Dual channel DDR3 Workstation, cloud computing, infrastructure m. michelotto

12. Magny Cours Q1 2010 Cores 8 -12 12 cores: Opteron 6174: mem DDR3 Quad-channel, cache 512 KB L2 per core, 12 MB L3 shared – 1900-2200 MHz at launch – Special Edition (SE) at 2300 MHz and High Efficiency (HE) at 1700 MHz later 8 cores from 2000 to 2400 MHz – TDP 85W (HE), 115 W (standard) 140W (SE) m. michelotto

13. T2 recent bids m. michelotto

14. HS06/node at CERN m. michelotto

15. CERN projections m. michelotto

16. The Worker node 2 socket had the best price/performances 1 socket could be cheaper? Blade or twin/dual twin Dual PSU not energy efficient and rather useless in the bulk WN HW RAID 1 very popular in INFN but is it a hard requirement or a plus? m. michelotto

17. Disk Server From the HEPiX site reports: Two approaches – Big SAN, a Fibre Channel Switch, several Storage Fronte End server – Many server with Direct Attached Storage (internal or in a separate box) m. michelotto

18. Disk in 2009 Cost/TB  TB per disk 2008 1TB SATA 2009 1.5 TB not very common 2009 2 TB very common m. michelotto

19. Disk 2010 Move to 2.5” 1 TB SATA 7200 rpm 2.5” 600 GB SAS 15000 rpm 3 TB in 3.5” SATA using HAMR (Heat Assisted Magnetic Recording) ? SSD ???

20. Prediction 1: SSD will be more cost effective in 2009 SSD predictions

21. Prediction 2: SSD will be bigger in capacity in 2015 SSD predictions