1. Associative Memory design for the Fast Track processor (FTK) at Atlas I.Sacco (Scuola Superiore Sant’Anna) On behalf Amchip04 project (A. Annovi, M. Beretta, F. Crescioli, M. Dell'Orso, P. Giannetti, M. Piendibene, I. Sacco, L. Sartori, R. Tripiccione) SIF Congress 2010, Sept 20-24, 2010, Bologna, Italy

2. Pattern Recognition using Associative Memory (AM) Associative memory used in very fast tracking in HEP A large bank with pre-computed low resolution tracks (patterns) AM [1] finds tracks during detector readout as “patterns matching the event”, called also “roads” Full resolution tracks (near offline quality) are extrapolated using fast track techniques inside the roads [2], where linearized fit can be performed.

3. The ATLAS Luminosity The existing ATLAS trigger does the needed track reconstruction in the level-2 farm, which will work well up to LHC design luminosity of 1  10 34. @SLHC Phase I luminosity (~ 3x LHC) → requires higly increase of pattern density keeping power consumption under control !! at LHC

4. AMChip Core One patternn Parallel comparison between the incoming hit coordinates with the stored patterns. Ability to correlate data received at different times. Fast response and high flexibility in data reception Output Bus

5. 90 nm Miniasic & Full custom Amchip04 Amchip03 180 nm std-cell technology used in CDF experiment 90nm technology Miniasic How to improve by a factor 2 pattern density while keeping consumption under control? 1.Full custom 2.Power saving technique: selective precharge

6. 90 nm Miniasic & Full custom (2) 1. Full custom Each full custom layer become a new standard cell:  std cell costraints & rules  Model for behavioral simulation  Model for timing simulation Full custom cells cover the green region Layout of a NAND CAM cell 32x8 layers in each block

7. 90 nm Miniasic & Full custom (3) 1. Power saving technique: selective precharge Mixing NOR and NAND cell: the Match-line is precharged ONLY if the first 4 bits have a match. Power reduction factor 3 Dovrebbe essere 16! ?? Sono 4 porte NAND e ciascuna ha una probabilita’ ½ di metchare, quindi 1/16 che metchino tutte e 4?

8. Design Framework Full custom layer

9. History and Perspective What is now in CDF :  180 nm technology  40 MHz clock frequency  1x1 cm area  5 Kpattern/chip with 6 Layers  Core voltage 1.8V What’s new in Amchip04Effect 90 nm technology Full custom Up to 1.5x1.5 cm area 100 MHz clock frequency Core voltage 1V Selective precharge Reduction of pattern area (1/4) Reduction of pattern area (1/2) More area available but higher consumption Faster but higher consumption Reduction of power consumption Reduction of power consumption (1/3) We could reach density of about 60 Kpattern/chip with 8 layers mantaining roughly the same power consumption (less than 2 W/chip)!!