1. Design of OCDMA Demonstrator Yun Ping Yang, Alireza Hodjat, Herwin Chan, Eric Chen, Josh Conway

2. Purpose To provide secure communications over optical channels Simple and scalable implementation with no performance degradation to traditional WDM schemes

3. Time-Wavelength Grid (WDM) A1 Wavelength 1 A2A3A4 B1 Wavelength 2 B2B3B4 C1 Wavelength 3 C2C3C4 C1 Wavelength 4 C2C3C4 Time

4. Random Wavelength Hopping A1 Wavelength 1 B2C3B4 C1 Wavelength 2 D2D3C4 B1 Wavelength 3 A2B3D4 D1 Wavelength 4 C2A3A4 Time

5. Random Grid Hopping A1 Wavelength 1 B2D4B1 A2 Wavelength 2 D2D3C2 B4 Wavelength 3 A3B3C4 D1 Wavelength 4 A4C3C1 Time

6. OCDMA Cryptographically secure (at physical layer) No collisions between data streams Efficient spectral usage (high performance)

7. 1:4 Detector    User 1 16X16 Switch 155MHz 1:16 16:1 16X16 Switch 16X16 Switch 16X16 Switch 16:1 User 2 User 3 User 4 Pat. Gen  de-Serializer Serializer 1:16 16:1 Pat. Gen 16X16 Switch 155MHz 2.5Gbps User 1 User 2 User 3 User 4 4:1 Modulator   Fiber 1:16 16:1 2.5Gbps 16X16 Switch   16X16 Switch 16X16 Switch de-Serializer Serializer 1:16 16:1 First Demonstration System

8. Switching Matrix Each switch is independently controlled by a single bit Output is permutation of input Permutation changes every clock cycle

9. Switching Elements 0101 0101 Code bit Code bit = 0 Code bit = 1 delay = 1/(155MHz) = 6.5ns delay = latency delay = 1/(155MHz) = 6.5ns delay < latency = 45.2ns Solid State SwitchDigital Pipelined switch

10. Solid State vs. Pipelined Switch

11. FPGA Implementation Timing requirements easier to meet Easier integration between matrix and code generator Implementation flexibility and reprogrammability

12. FPGA Architecture 16 lvds data pairs Lvds clock Start Load seed Seed input (serial) 16 lvds data pairs Lvds clock Pll locked Valid data Reset Config mode LVDS input PLL Switching Matrix LVDS Output Delay Module LFSR System clock

13. Switch matrix (encrypt) Lfsr [c 55 … c 0 ] z2z3z4z5z6z c 55 c 53 c 52 c 46 c 47 c 45 c 49 c 44 c 51 c 43 c 50 c 48 c 41 c 40 c 42 c 33 c 32 c 35 c 34 c 36 c 39 c 38 c 37 c 25 c 24 c 27 c 26 c 28 c 31 c 30 c 29 c 17 c 16 c 19 c 18 c 20 c 23 c 22 c 21 c9c9 c8c8 c 11 c 10 c 12 c 15 c 14 c 13 c1c1 c0c0 c3c3 c2c2 c4c4 c7c7 c6c6 c5c5 z2z3z4z5z6z c 25 c 24 c 27 c 26 c 28 c 31 c 30 c 29 c 54

14. Switch matrix (decrypt) Lfsr [c 0 … c 55 ] z2z3z4z5z6z c 55 c 53 c 54 c 52 c 46 c 47 c 45 c 49 c 44 c 51 c 43 c 50 c 48 c 41 c 40 c 42 c 33 c 32 c 35 c 34 c 36 c 39 c 38 c 37 c 25 c 24 c 27 c 26 c 28 c 31 c 30 c 29 c 17 c 16 c 19 c 18 c 20 c 23 c 22 c 21 c9c9 c8c8 c 11 c 10 c 12 c 15 c 14 c 13 c1c1 c0c0 c3c3 c2c2 c4c4 c7c7 c6c6 c5c5

15. Delay Module LFSR (56 bits) Each line corresponds to 8 consecutive signals from adjacent LFSR registers 101010101010101010101010 Encrypt/ decrypt test

16. Code Generator: LFSR Galois implementation taps: [56, 7, 4, 2, 0] –gives maximal code length g 7 = 1g 4 = 1g 0 = 1g 56 = 1 … … Output control bits g 2 = 1

17. Design Methodology.edn.ucf.v.edif.mcs + Bitstream Data for FPGA Synthesis (Xilinx ISE 5.1) Place & Route (Xilinx ISE 5.1) Verilog Hardware description and functional simulation using ModelSimXE 5.6a Reports Timing information Resource usage information Implementation Board level testing

18. Test Strategy (Functional Simulations) Code generator –software version (in C) used to generate expected data of hardware Switching Matrix (static) –two switch matrices connected together with static control bits; random input stream compared with resulting output stream Switching Matrix (dynamic) –control bits of matrices connected to code generator through delay module; random input stream compared with resulting output stream

19. Dynamic Switch Matrix Simulation Transmit: 6 clock latencyReceive: 7 clock latency

20. Implementation Details Verilog code600 lines XC2V1500 FPGA Area 260 slices (3% capacity) Maximum critical path5.2 ns (192 MHz) LVDS pin capacity Avnet Board 155% (34 / 22) LVDS pin capacity Insight Board 81% (34 / 42)

21. Serializer / Deserializer Deserializer Serializer PECL 2.5 Gbps Output clock eye diagram lvpecl.jpg 16 lines 2.5 Gbps155 Mbps LVDS 15 bits ‘0’

22. Future Work LVDS interface Sender / Receiver Synchronization Cryptographically secure code generator

23. LVDS Interface for FPGA DLL XC2V1500 FPGA DeserializerSerializer Clock signal must be transmitted in separate differential pair to avoid clock skew Clock signal must be common for all components

24. Encrypt / Decrypt Synchronization EncryptChannelDecrypt EncryptChannelDecrypt EncryptChannelDecrypt Tokens control starting and stopping of code generators Start code gen Stop code gen

25. Code Generator: AES Cryptographically Secure Pseudo-random number generator Advanced Encryption Standard (AES) in Counter mode of operation Encryption at the rate of several Gbits/sec using 128-bit key and data length Pipelining and loop unrolling techniques