1. Electronics Department Amsterdam 5-July-2010 Sander Mos 1 Status and progress of NIK* Logic WPFL - 5 July 2010 Amsterdam * Network Interface Kit

2. Electronics Department Amsterdam 5-July-2010 Sander Mos 2 Node Interface Kit overview shore DM laser R-EAM PIN CW laser Mem PIN 311 Mhz clock GbE 311 Mhz clock GPS Receiver and reference clock SPARK Light e.g. OM “Heartbeat” with embedded SC up to 12x 10 Gb/s 10 Gb/s Continuous wave laser PMT data TTC Gen. I/O Includes basic firmware serving the physical layer end-node The NIK board will work on every optical network connection and has the opportunity serving the physical layer of the optical network. For general KM3NeT use the functionality in the node hardware is extended and established after meeting results. FPGA Passive Optical Network SPARK upgrade to bidirectional (transparent for the data transmission format) DDR3 Mem FPGA + SOC If needed

3. Electronics Department Amsterdam 5-July-2010 Sander Mos 3 Electronics subsea Development board Stratix-4 Receive PMT data SerDes + clock GPS-clock for “heartbeat” generator R-EAM + driver PIN + TIA and LimAmp R-EAM + driver PIN + TIA and Lim.Amp. SPARK extension currently Reproduction driver cards Reproduction receiver cards Timing adapter module Design +schematic entry Overview: SLB layout in OM Now ex R-EAM, PIN and related electronics NIK sub-sea development board Connected to: Octopus board FPGA Readout PMT’s I2C temp sensors I2C instruments (place holder) photonics and related hardware Among: Direct conn to Devpl. Stratix 4 2 ADC (current/voltage) Leds/switches Scott chip connector NIK Subsea devlop. board Later: integration in Sphere Logic Board currently Example of the NIK modular approach NIK can be helpful to determine final functionality in the total KM3NeT DAQ system Electronics on-shore Interface op/el v.v. PON

4. Electronics Department Amsterdam 5-July-2010 Sander Mos 4 All I/O 3V3, 2V5, 1V8 or LVDS. Preferred I/O 2V5 KM3NeT NIK Node FPGA Altera Stratix IV EP4S40G2 POWER Board CDR R-EAM driver PIN R-EAM 3D COMPASS HMC5843 ? ADC LED Beacon PMT control PMT LVDS signals Acoustic Sensor Optical Network Sensors: -Temperature? -Voltage? -Water? 3”or 8” PMT’s I2CI2C I 2 C Bus SPI 625Mbps 10Gbps 31 LVDS signals for 3” PMT’s 18.....signals for 8” PMT’s 10 - 14V 1V8, 3V3, 5V, LEDBEACON Control 2 connectors for 2 x SCOTT Octopus Board Mezzanine Boards 3D G-sensor ADXL345 ? 512 Mbit Flash Mem. EPM2210 CPLD for FPGA Config. SPI SPARK 128MB DDR3 Memory.

5. Electronics Department Amsterdam 5-July-2010 Sander Mos 5 OM’s Shore station Downstream data rate Total 625Mbps shared Upstream data rate 10Gbps for each OM Shore station OM’s Different data load and speed from shore to seabed and v.v. The detector has an asymmetric upload and download DataStream  Slow Control data is available for OM control.  To reduce the number of fibers, the slow control commands are send by broadcast.  The shared data rate is 625Mbps  (6000 OM’s resulting in 10Kbps per OM) The broadcast structure also allows the use of a single or central system clock at the entire detector The data path from each OM to the shore will be a point-to-point connection using optical channels.

6. Electronics Department Amsterdam 5-July-2010 Sander Mos 6 Extended logics Original plan: design and realize electronic hard and firmware for readout of 31 PMT’s with an event time resolution < 1ns and storage of the data “on shore” (Instrumentation interfacing and others to be determined later.) Following requests of the KM3NeT consortium the design has been extended. Added to the basic configuration: 2 connectors for interfacing 2 SCOTT chips (for 31 PMT channels) 128MB DDR(3) memory on request for running VX-Works Remote configuration of FPGA with the possibility by adding a SOC* SOC and memory makes store and forward data transfer inherently possible Extra I/O connectors for LED beacon, acoustics, compass, tilt meter…. If wanted: Synchronous data readout still remains possible Warning: Electrical power consumption per optical module strongly depends on the complexity of the implemented local logic *SOC = System On Chip – resides inside the FPGA (implemented by a FPGA IP core)

7. Electronics Department Amsterdam 5-July-2010 Sander Mos 7 Status of the NIK evaluation board NIK-Power Design and board realization finished, PCB has been assembled, waits for tests The board generates the local voltages for the FPGA, the PMT’s and sensors. Local generated voltages are 5V, 3V3, 3V3 analog, 2V5, 1V8. Board input 10-14V supply voltage from the DC-DC converter that resides in the breakout boxes and is part of the vertical structure Converter efficiency >90% @ max ~25 W NIK-Logic -All components are selected and ordered. -Except for the FPGA, 80% of the components are already available at Nikhef -Schematic entry is in progress. -Estimated total power consumption of the logic board is ~ 10 W Foreseen board realization time in August 2010 has been extended because of: -new CAD software implementations at Nikhef -the addition of the SCOTT interface, -128MB DDR memory needed for local Operating System

8. Electronics Department Amsterdam 5-July-2010 Sander Mos 8 The mechanical Logic-board equivalent also serves: - Connect and test simultaneously the 2 Octopus boards during OM assembly - Verification of the “Manhattan” profiled board cooling design - Testing and validating the NIK-Power figures No logic has been implemented For form factor verifications in the Multi PMT OM a mechanical Logic-board equivalent has been realized

9. Electronics Department Amsterdam 5-July-2010 Sander Mos 9 NIK Firmware status  Basic firmware is currently being written in VHDL by Albert Zwart.  The VHDL code is now used as a place holder to interact with schematic entry and simultaneously it can do basic verifications.  Simulation of the VHDL parts works  The code is being tested on a Stratix IV evaluation board with memory. (picture below)  Two weeks preparation time were needed to manage the addition of DDR3 memory and the 31 PMT LVDS inputs to the NIK core.  Before realization of the hardware, the NIK logic board will only contain the minimal firmware making testing of the serial interfaces and PMT readout possible.  The NIK will be configured hardware wise.  The NIK allows the choice for preferred firmware and has to be extended to a full working firmware. E.g. SOC implementation, the use of Ethernet data messaging, etc. Extension cards available 2 nd Stratix IV evaluation board @Nikhef In use for LHCb

10. Electronics Department Amsterdam 5-July-2010 Sander Mos 10 The NIK is a development tool that can help to scale down after development to a dedicated storey logic board and the NIK-logic board is not meant to be the final storey logic board Examples: Downscaling to a final Storey Logic board the large Stratix IV FPGA can be replaced by a small FPGA by using an external SOC. Implementing a separate fast serializer*. connected to a Xilinx Virtex 5+ The NIK is needed for further Optical Network developments and tests. When the total OM power is exactly known, only than the final power board for a storey can be definitively designed. Finally all the seabed electronics must be reviewed and optimized for highest efficiency and lifetime. For the moment the NIK can handle many different system implementations due to its flexibility by firmware configuration *Texas Instruments has a 10Gbit serializer available for €45 (TLK10021) If 10 Gbs data transfer is preferred Conclusion

11. Electronics Department Amsterdam 5-July-2010 Sander Mos 11 Thank you for your attention

12. Electronics Department Amsterdam 5-July-2010 Sander Mos 12