1. Taeho Kgil, Trevor Mudge Advanced Computer Architecture Laboratory The University of Michigan Ann Arbor, USA CASES’06

2. Outline Motivation Introduction FlashCache Architecture & How It Works Experimental Setup Result Conclusion and Future Work

3. Motivation DRAM idle power contributes to a large portion of overall system power. The authors propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Furthermore, reads are more frequent than writes in web server applications, these characteristics make a strong case for using flash memories as a secondary file buffer cache.

4. Introduction

5. The authors observe an access latency of tens to hundreds of microseconds can be tolerated when accessing a large part of a file buffer cache without affecting throughput.

6. FlashCache Architecture

7. FlashCache Hash Table Wear-level Status Table Maintains the number of erases and writes performed on a logical block Flash memory controller with DMA support To handle DMA transfers form DRAM to flash memory

8. How FlashCache works When a file I/O is performed, the OS searches for the file in the primary page cache located in DRAM Hit in DRAM: the FlashCache is not accessed at all Miss in DRAM: the OS searches the FCHT to determine whether the requested file currently exists in secondary page cache Hit in FlashCache: a flash memory read is performed Miss in FlashCache: a logical block is selected for eviction. The hard disk drive content is coped to the primary page cache in DRAM. Finally, we schedule a writeback of the hard disk drive content to flash memory using DMA.

9. Experimental Setup A full system architectural simulator called M5 Evaluate full system level performance Add timing and power models of flash memory to M5 A web server connected to multiple clients is modeled Server benchmarks SURGE SPECWeb99

10. Experimental Setup

11. Result Network Performance

12. Result Overall main memory power No power management Ideal power management FlashCache

13. Conclusion and Future Work The simulations shows more than a 2.5x reduction in overall main memory power with negligible network performance degradation. Future work will investigate the bandwidth requirements and endurance requirements for adopting flash memory for other types workloads found in other application domains.