1. 1 WA105 General Meeting CERN, 21/1/2015 Status of charge readout FE electronics and DAQ Dario Autiero,E.Bechetoille, D.Caiulo, B.Carlus, L. Chaussard, Y. Declais T. Dupasquier, S. Galymov, C.Girerd, J. Marteau, H.Mathez, E. Pennacchio IPNL Lyon

2. 2 ASIC cryogenic amplifiers with double slope gain Adapted to LEM dynamics like previous version 1200 fC single slope Larger gain up in the few mip region, kink point point at 10 mip and reduced gain by a factor 3 up to 40 mips max dynamic range  Submitted for a CMP run at the end of September 2014  Received beginning of January 2015. Tests starting now  Replace feedback capacitor of the preamplifier with a MOS capacitance which changes the C value above a certain threshold voltage (gain ~ 1/C). Selectable double time constant in discharge or single one with diode +resistor to keep constant RC Double slope implementation (starting from previous ASIC version):

3. 3 Test of surge protection components on FE cards for the cryogenic ASICs Built a « Spark Box » to produce controlled “sparks” with: -HV PS (adjustable discharge amplitude 50V-3 kV) -Reed HV relays to control fast charge/discharge -HV capacitor 2.5 nF -Integrated breadboard to test various surge protection solutions on different loads -HV probe (1/1000) + digital scope to measure time development of sparks Example: comparison of 1 KV discharge on GDT (delayed cutoff and V reaching ~1 KV on load resistor of 124 Ohm) and MOV varistor (earlier varistor cutoff  limiting to 500 V the discharge amplitude)  Characterization studies of surge protection components under finalization + long term degradation study and behavior at cold Measurements of sparks from LEMs (see presentation of 20 November 2014)  EPCOS GDT slow response wrt spark time development not limiting peak voltage on amplifier circuit RC discharge

4. 4 AMC digitization card Board characteristics – µTCA standard (double width, full height) – 64 input channels (2V / 14 bits / 2.5 Msps to 20 Msps) – Control through MCH 1GbE backplane link port 0/1 – Data transmission through 10GbE backplane and MCH 10GbE SW – Local buffer dual port memory (512K + 256K 18 bits) 12288 samples per channel. (or more if necessary to be confirmed )

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7. 7 Data acquisition demonstrator Based on µTCA AMC S4AM from Bittware FMC mezzanine board with 64 ADC channels Control through GbE Data transmission through 10GbE AMC S4AM 64 ADC ch FMC mezzanine

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9. 9 Card produced and tested

10. 10 DAQ board demonstrator status FMC with 64 ADC / analog part for inputs: Fully tested and operational Slow control GbE µTCA port 0 : Tested, operational, (optional IPBUS missing) 10 GbE data transmission : under development Firmware ADC serial receivers OK GbE slow controlOK GbE data transmission OK Zero suppressionunder development 10 GbE management under development Data acquisition protocolunder development Final architecture – Low cost FPGA choice (Cyclone V ?) To be defined – Memory choice (Dual port switchable bank, QDR or others) To be defined 64 ADC channels Demonstrator fully operational in GbE FPGA firmware already tested and dimensioned for the ADC DAQ, to be completed for 10 GbE data transmission part and zero supp.

11. 11  TCA-DAQ architecture Clock Splitter x14

12. 12 DAQ timing-trigger integration Preliminary general scheme (shown at previous meetings) CC 1CC 2 CC 12PMC PC Event Building CC 6 CC 7 6 10 GbE links + 2 spares Bittware card 1Bittware card 2 7 10 GbE links + 1 spares Meinberg GPS Clock Analog FO x14 Clock MCH PCI timing card Clock Time Beam window NIM signal every 20 s Beam Trigger counter NIM signal ~ a few 100 Hz Charge readout Light readout

13. 13 Time distribution: (shown at previous meetings) 1)A Fan-out distributes the analog clock signal generated by the Meinberg to the 12 charge readout crates (CC), to the PMT readout crate (PMC) and to the timing card in the event building PC 2)The timing card in the PC receives the time stamp info (Unix time) from the Meinberg 3) Sync. Data are sent every second to the micro-TCA crates: 12 CC and 1 PMC, they go down via the 10 GbE link, where there is practically no bandwidth used, the synchronization accuracy should be such as to align the 400 ns samples together 4)In each micro-TCA crate there is a custom MCH which makes the analog signal coming from the Meinberg clock fan-out available on the backplane 5)The bittware cards receive data aligned in time from the CC and the PMC (the relative internal alignment in time of the PMC data can be better than the one needed to align the 400 ns samples from different channels but in absolute these data will have an alignment compatible with the 400 ns samples) Details

14. 14 Event Building (shown at previous meetings)  The event building PC (EVPC) includes the two bittware cards and the timing card. The timing card provides the absolute time to the cycles and also time stamps the NIM signal of the beam cycle occurring every 20 s and it treats it via an interrupt. The beam window is opened for a few seconds every 20 s  This is a test-beam so during the beam time window we will have also the NIM signal from a trigger counters (a piece of scintillator + PMT + discriminator) placed on the beam-line. The instantaneous charged particles rate during the beam window of 3 s will be of a few hundreds hertz. This NIM signal is the real trigger during the beam window, independently of the PMTs and it has to be time-stamped by the timing card  The EVPC will define a trigger condition by treating the PMT data and the beam window + trigger counter info in the bittware card. During the beam window the trigger is given by the trigger counter (we have to understand if we want also conditions on the PMTs but in principle they should not be necessary). For the cosmics (out of the beam window) a complex condition can be defined by requiring several PMTs in coincidence in a given time window and above certain thresholds.  The trigger is sent down via the 10 GbE link to the CC which digitize the data in a circular buffer. When the trigger is received a drift window starting from the time of the trigger (all the system works on a common time base) is transmitted to the EVBPC. No other triggers are accepted until the drift window is transferred however the PMT data are written Details

15. 15 Integration of the PMT readout: (shown at previous meetings) 1)The PMC will be an independent micro-TCA crate not to interfere with the CC data transfer bandwidth 2)This crate will host a MCH receiving the analog clock signal from the FO and making it available on the backplane 3) The PMC crate will host the cards receiving the data from the FE digitization cards reading the PMTs 4)The digitization cards will time stamp the data on the basis of the common time- stamp and transmit them to the EVPC via the 10 GbE optical link which will be used in the opposite direction to receive the sync patters for synchronization. 5)The data format from the charge AMC includes already a time stamp. A general DAQ time stamp has to be defined to handle also the internal time resolution of the PMT readout which is more precise of the general sync signal used to align the 400 ns samples. This could be done for instance by adding another timing word for the internal alignment of the PMT data with better accuracy. This accuracy can then be exploited by the EVPC in order to compute the coincidence 6)The trigger is computed at the level of the EVPC and transmitted via the 10 GbE links to the CC 7)Once the data transfer for a drift window is opened no other triggers are issued but the PMT data sent from the PMC to the EVPC are stored in any case 8)The development of the PMC can go in parallel to the one of the CC Details

16. 16 Timing and Synchronization implementation 2 options : 1 => Custom implementation, like in general scheme presented at past meetings, based on analog clock distribution + PTP packets exchange or other 2 => White Rabbit based (Preferred choice at the moment in order to reduce design work and use large part of commercially available WR components under the OPEN HARDWARE licence) (White Rabbit is an evolution of the synchronization scheme based on synchronous ethernet + PTP which was previously developed at IPNL in 2008)

17. 17 White Rabbit based time distribution scheme WR MASTER WR SWITCH MASTER CLOCK µTCA Shelf WR slave µTCA Shelf WR slave µTCA Shelf WR slave µTCA Shelf WR slave Clock + time GbE Clock + Time AMC GbE AMC PC WR slave

18. 18 White Rabbit based scheme AMC DAQ BOARD AMC DAQ BOARD AMC DAQ BOARD Gbe (White Rabbit) Custom Clock Mezzanine (WR slave) NAT MCH clock time - Commercial white Rabbit Slave Node Firmware already exists - µTCA MCH Mezzanine implementation need to be developed

19. 19 Trigger distribution scheme NAT MCH Mezzanine clock AMC ADCs 10GbE Event building PC NAT MCH Mezzanine clock AMC ADCs Bittware boards 10GbE Bittware boards NAT MCH Mezzanine clock µTCA LEM readout µTCA PM readout 10GbE AMC PMs Trigger Board Trigger Board Beam trigger Bittware boards µP bocard Light trigger Processing

20. 20 Trigger development -TO DO : -PC timing/trigger board definition and design, employ commercial board ? -Trigger distribution path : via 10GbE data links or other dedicated path ? -Trigger input to AMC and AMC internal treatment of triggers for DAQ data flow (in case of zero suppression or no zero suppression modes) -Light signals processing to define light trigger: where to do it (PMTs uTCA crate processor or event building PC) ?

21. 21 Schedule: goal mass production in autumn 2015 -AMC digitization board - Board final design march / April 2015 -Board prototype submission : May 2015 -Board prototype test : June/July 2015 -Eventually 2 nd version August / September -PC Timing/trigger board (if no commercial solution) - Board design September 2015 -Board prototype submission : December 2015 -Board prototyope test : January 2016 -NAT MCH clock mezzanine for timing/trigger - Board design May 2015 -Board prototype submission : june 2015 -Board prototyope test : september 2015

22. 22 Conclusions:  Planned end of developments for ASIC FE and DAQ by fall 2015  goal for massive production to happen by end of 2015/first part of 2016  Double slope version of ASIC FE (16 channels, LEM dynamics) submitted in September received in January and tests starting now  Surge protection components for FE cards under test in dedicated characterization bench  DAQ AMC demonstrator: ADC FMC mezzanine board received and tested. Analog input stage characterized and OK. ADCs operational, related firmware developed.  AMC data transmission and zero suppression firmware under development  Starting Definition of the schemes for trigger and clock distribution to AMC  Possible clock distribution scheme using White Rabbit components  Starting definition of massive data storage  Dedicated TB meeting will be organized on the issues of Charge/Light readout integration, clock distribution and triggers distribution/handling