1. Presented By Aditya Dayal ITM University, Gwalior

2. Introduction to the AMBA Buses: The Advanced Microcontroller Bus Architecture (AMBA) specification defines on chip communications standard for designing high- performance embedded microcontrollers. The distinct buses are defined within the AMBA specification: Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB) Advanced eXtensible Interface (AXI)

3. HISTORY OF AMBA PROTOCOLS Performance 199920031995 Time APB ASB AHB AXI

4. APPLICATIONS Mobile segment Smart phones Portable Audio Portable Media Voice phone Digital camera Home segment DVD Players Set top box Portable gaming HDTV

5. Overview of the AMBA family specifications AHB (Advanced high-performance bus) Highest performance bus in the AMBA family before AXI Suitable for medium complexity and performance connectivity solutions AHB Lite Subset of the full AHB spec Intended for use in designs where only a single master is used ASB (Advanced system bus) The AMBA ASB is for high-performance system modules ASB also supports the efficient c onnection of processors, on-chip memories and off-chip external memory interfaces with low-power peripherals. APB(Advanced peripheral bus) General purpose I/O Register based peripherals such as timers,interrupt controllers,UART etc. Connected to system bus via a bridge, helps to reduce system power consumption Easy to interface to, with little logic involved.

6. AMBA 2.0 application space Serves as a frame work for Soc designs System-on-a-chip(SOC) designs On-chip bus for ARM processors

7. A typical AMBA-based microcontroller: High- bandwidth memory interface High- performance ARM processor PIO DMA bus master High-bandwidth on-chip RAM Timer UART keypad BRIDGEBRIDGE AHB/ASBAPB Figure:The APB in a typical AMBA system

8. AMBA APB: The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The AMBA APB is used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface. Low power Latched address and control Simple interface Suitable for many peripherals

9. AHB vs APB AMBA AHBAMBA APB FeatureHigh performance Pipelined operation Multiple bus masters Burst transfers Spilt transactions Single-clock edge operation Low power Latched address and control Simple interface Single-clock edge operation ComponentsAHB master AHB slave AHB arbiter AHB decoder APB bridge APB slave

10. Micro architecture -Master APB bridge PRDATA PADDR PWDATA System bus slave interface Read data reset clock PRESETn PCLK PSEL1 PSEL2 PSELn PENABLE PWRITE SELECTS STROBE ADDRESS AND CONTROL WRITE DATA

11. Micro architecture -SLAVE APB slave PADDR PWDATA PRDATA SELECT STROBE ADDRESS AND CONTROL RESET CLOCK WRITE DATA PSELx PENABLE PRESETn PCLK PWRITE READ DATA

12. APB signals APB signals list Signal nameSizeDirectionDescriptionSignal H/L PCLK1InputBus clock –all transfers are timed on the rising edge High PRESETn1InputBus reset-active LOW this signal normally connected directly to system bus reset Low PADDRUpto 32 bitsInputAddress bus – upto 32- bits wide driven by the peripheral bus bridge PSELx1InputSlave device select- from the secondary decoder within the peripheral bus bridge indicates a data transfer is required High

13. APB signals (cont’d) APB signals list Signal nameSizeDirectionDescriptionSignal H/L PENABLE1inputEnable-indicates the second cycle of a transfer, rising edge of PENABLE occurs in the middle of a transfer High PWRITE1inputWrite/read –when HIGH write access and when LOW a read access High/low PRDATAUpto 32 bitsoutputRead data-bus is driven by the selected slave during read cycles High PWDATAUpto 32 bitsinputWrite Data –bus is driven by the peripheral bus bridge unit during write cycles High

14. APB FSM IDLE PSELx=0 PENABLE=0 SETUP PSELx=1 PENABLE=0 ENABLE PSELx=1 PENABLE=1 transfer No transfer transfer

15. APB FSM State diagram of peripheral bus activity IDLE The default state for the peripheral bus SETUP The bus moves into this state when a transfer is required The bus remains in the SETUP state for one clock and always move to the ENABLE state PSELx is asserted ENABLE PENABLE is asserted the address, write and select signals all remain stable during SETUP->ENABLE

16. Write Transfer Timing

17. Write cycle Write starts with address, write data, write signal and select signal, all changing after the rising edge of the clock After the following clock edge the enable signal PENABLE is asserted, and this indicates that the ENABLE cycle is taking place To reduce power consumption the address and the write signal will not change after a transfer untill the next access occurs

18. Read Transfer Timing

19. Read cycle The timing of the address,select and strobe signals are all the same as for the write except PWRITE Read,the slave must provide the data during the ENABLE cycle Data is sampled on the rising edge of clock at the end of the ENABLE cycle

20. Thank you