1. 1394 H/W and OHCI 2002. 2. 27 Gi-Hoon Jung

2. 2002/01/162 Agenda Overview of the VITANA board OHCILynx PCI-based Host Controller Overview of the OHCI Spec Remarkable point

3. VITANA and OHCILynx

4. 2002/01/164 VITANA board Philips Full Duplex A/V Link Layer IEEE1394 Reference Design Kit v1.0 Testing & Evaluating 1394 environment PDI1394L21 –1394 AV Link layer controller –H/W support for IEC61883 interface –8051 compatible Host Controller interface –400Mbps capable PDI1394P11 –3 ports, up to 200Mbps capable

5. 2002/01/165 Application Diagram of PDI1394L21 MPEG or DVC Decoder MPEG or DVC Decoder PDI1394L21 AV Link PDI1394Pxx PHY 8051 compatible Host Controller 8bit AV Interface 8bit Host Controller Interface 1394 Cable Interface

6. 2002/01/166 Functional Block Diagram of VITANA v1 Host Controller  Async packet, Register read & write AV CPLD  Iso packet 8051 Family CPU LLCPHY ROM & RAM AV CPLD AV Headers 1394 Ports Address Decoder GAL

7. 2002/01/167. Circuit component 1394 PHY1394 AV LLCAV CPLD8051 family64k*4*2 RAM 64k*8 ROM Two AV Connection Headers Three 1394 Ports Serial Port Addr Decoding GAL Reset State Machine GAL

8. 2002/01/168 TI OHCILynx Host Controller TSBKOHCI403 1394a compliant, 400Mbps capable TSB12LV23 –PCI based 1394 Host Controller –Link Layer Controller –Up to 400Mbps TSB41LV03A –1394a 3-port Cable Transceiver/Arbiter –Up to 400Mbps

9. 2002/01/169 TSB12LV23 Block Diagram

10. 2002/01/1610

11. Overview of the OHCI spec

12. 2002/01/1612 Introduction of the OHCI Open Host Controller Interface Spec –Latest release v1.1 at Jan. 6. 2000. Implementation spec of the Link layer Support the transaction and BM layers DMA engines for high-performance data transfer and a host bus interface H/W description and S/W interface

13. 2002/01/1613 System Requirements It just need the same programming model Host Controller shall be able to –Initiate accesses of host system memory –Modify system memory with byte granularity –Signal an exception/interrupt to the host CPU –Access 32bit registers with endian neutral and atomic –No 8-bit or 16-bit access to registers are supported

14. 2002/01/1614 1394 Protocol Layer ?

15. 2002/01/1615 OHCI H/W description

16. 2002/01/1616 Address Space of 1394 Spec

17. 2002/01/1617 OCHI Node Offset Address Map CSR Space (256MB) Upper Addr Space (3.75GB) Middle Addr Space (Almost 256TB) Low Addr Space (default 4GB) 48’h0000_0000_0000 48’hFFFE_FFFF_FFFF 48’hFFFF_0000_0000 48’hFFFF_EFFF_FFFF 48’hFFFF_F000_0000 48’hFFFF_FFFF_FFFF physicalUpperBound-1 physicalUpperBound Default :0001_0000_0000 Physical Request/Response S/W processing space (Good for TCP/IP) S/W processing space (H/W Stop & Wait capable) Nearly S/W processing space (some physical)

18. 2002/01/1618 OHCI S/W interface 3 Basic Means –Registers OHCI ’ s registers are mapped into the host ’ s address space (2KB) –DMA operation Context Control, CommandPtr Register DMA Context and Descriptor Block –Interrupts IntEvent and IntMask registers

19. 2002/01/1619 Types of DMA functionality General purpose –Async & Iso transmit and receive Physical DMA –Inbound bus bridge function A separate write buffer –For the received self-ID packets Mapping between a 1KB block in system mem and the first 1KB of 1394 configuration ROM

20. 2002/01/1620 1394 Packet and Descriptor Block 1394 Packet –16 ~ 4096 Bytes / Packet (400Mbps) DMA Descriptor Block –A group of descriptors(16 or 32 Bytes) that are contiguous in host memory –I/O Type: more, last, immediate –Example: AR DMA Input_more descriptor

21. 2002/01/1621 Common DMA transfer process Context Control Register CommandPtr Register Transaction sequence (by S/W, by H/W) spd event code active dead wake run 15 1211107 54 031 descriptorAddress [31:4]Z value 031

22. 2002/01/1622 Work Types Bus Initialization  Self Identification Asynchronous Transfer –Physical request, self-ID phase packet –Asynchronous request/response Isochronous Transfer –Isochronous request/response

23. 2002/01/1623 DMA summary

24. 2002/01/1624 Packet receive mode Buffer Fill mode

25. 2002/01/1625 Packet-per-Buffer Mode

26. 2002/01/1626 Dual-Buffer Mode

27. 2002/01/1627 Isochronous Transmit DMA

28. 2002/01/1628 Iso Transmit Cycle Loss Example

29. 2002/01/1629 Self-ID Receive DMA Self-ID stream –63 devices * 4 packets/device * 2 quadlets/packet = 504 quadlets (Max) SelfID Buffer Pointer Register SelfID Count Register

30. 2002/01/1630 Remarkable point OHCI 는 동일한 programming model 을 추구 함 Host memory 억세스 방식으로 1394 자원 접근 현재는 PCI 기반의 제품만 구현되어 있음