1. EE 653: Group #3 Impact of Drowsy Caches on SER Arjun Bir Singh Mohammad Abdel-Majeed Sameer G Kulkarni

2. Outline Problem Statement SEU in SRAM Cell SER Analysis Model Key Issues and Challenges Current Progress and Future Work References 2Impact of Drowsy Cache on SER

3. Problem Statement Power Wall – Large Caches consume lot of static power. – Drowsy cache: Enables to Reduce the static leakage power, without data loss. Impact of technology scaling on SER needs to be studied Circuit SER α Flux x Area x e (-Qcrit/Qs) -[1] Q crit : is the minimum amount of charge needed to upset or flip a bit – capacitance holds the charge will become less – Q crit decrease with technology scaling. – Q crit decrease while we are working in drowsy mode.. Q crit = C node x Vdd + I DP x T F -[2] 3Impact of Drowsy Cache on SER

4. SEU in SRAM Cell Impact of Drowsy Cache on SER4

5. SER Analysis Model 5 MASTAR5 Tool: Provides the Process parameters for a given Technology. SER MODEL: computes the probability of “bitFlipRate” for a SRAM cell. PARMA MODEL Calculates and classifies the FIT rate into SDC and DUE. SIMULATOR Simple-scalar 3.0 integrated with drowsy cache and PARMA model. Impact of Drowsy Cache on SER

6. ISSUES AND CHALLENGES Extracting the Technology related parameters from MASTAR5. – For a given technology values differ in different roadmaps and different predictive models. – Differences observed in values of various profiles (LP, HP) for a same technology. Running the spice simulation to model the precise values for pmos current and Q crit – Lab setup enable to test only for the 180nm technology (TSMC18-LP). – Parameters cannot be experimentally verified for other technology scales. Running the Test benchmarks on a instruction wise simulator. – Current model runs on a cycle-by-cycle mode: this takes too much of time. Verifying the correctness of the obtained results. – No data available to verify the SER of Drowsy Cache. Virtualization and Beyond6

7. Current Progress and Future Work 7Impact of Drowsy Cache on SER Technology (nm)6545322218 Vdd (v) 1.20.900.800000.70000 Qcritical (fC) 0.57800320.2832610.1577340.0859980.069369 Qs (fC) 9.534727.1941125.5406574.1582653.565785 SRAM AREA (6T) 0.616850.295650.1495040.0706640.047304 FLUX 0.00565 SER (per Cell) 0.00328030.0016060.0008210.0003910.000262 SER data for different process technologies. We converted the simulator from cycle-by-cycle mode running on Sim- outorder to work on instruction-by-instruction mode on Sim-cache. In future Run the standard benchmarks in drowsy and normal mode and compare the results for different drowsy levels and drowsy window modes.

8. References [1] M. Powell et.al, Gated-Vdd: A Circuit technique to reduce leakage in deep submicron cache memories. Proc. Of Int. Symp. Low Power Electronics and design, 2000. [2] K. Flautner, et.al, Drowsy Caches: Simple Techniques for Reducing Leakage Power. Proc. of the 29 th annual Int. Symp on Computer Architecture (ISCA 02). [3] S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, and T. Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. Proceedings of the 36 th Annual International Symposium on Microarchitecture, pages 29 - 40, Dec 2003. [4] S. Mukherjee Architecture Design for Soft Errors [5] H. Mostafa, M. Anis, M. Elmasry. Comparative Analysis of Process Variation Impact on Flip-Flops Soft Error Rate. [6] P. Hazucha and C. Svensson, Member, IEEE. Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate [7] Accurate Reliability Benchmarking of Caches with PARMA [8] A. J. Johnston. Scaling and Technology Issues for Soft Error Rates [9] V. Degalahal, L. Li, V. Narayanan M. Kandemir, M. J. Irwin. Soft Errors Issues in Low-Power Caches [10] T. Heijmen, D. Giot, P. Roche. Factors that impact the critical charge of memory elements. [11] S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. Cacti 5.1. 8Impact of Drowsy Cache on SER