1. EE141 Arithmetic Circuits 1 Chapter 14 Arithmetic Circuits Rev. 1.0 05/12/2003

2. EE141 Arithmetic Circuits 2 A Generic Digital Processor

3. EE141 Arithmetic Circuits 3 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

4. EE141 Arithmetic Circuits 4 An Intel Microprocessor Itanium has 6 integer execution units like this

5. EE141 Arithmetic Circuits 5 Bit-Sliced Design

6. EE141 Arithmetic Circuits 6 Bit-Sliced Datapath

7. EE141 Arithmetic Circuits 7 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

8. EE141 Arithmetic Circuits 8 Adders

9. EE141 Arithmetic Circuits 9 Full-Adder

10. EE141 Arithmetic Circuits 10 The Binary Adder

11. EE141 Arithmetic Circuits 11 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete =A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for

12. EE141 Arithmetic Circuits 12 The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 A 3 B 3 S 3 C i,0 C o (  C i,1 ) C o C o,2 C o,3 t d = O(N) t adder = (N-1)t carry + t sum

13. EE141 Arithmetic Circuits 13 Complimentary Static CMOS Full Adder 28 Transistors

14. EE141 Arithmetic Circuits 14 Inversion Property

15. EE141 Arithmetic Circuits 15 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

16. EE141 Arithmetic Circuits 16 A Better Structure: The Mirror Adder

17. EE141 Arithmetic Circuits 17 Mirror Adder Stick Diagram

18. EE141 Arithmetic Circuits 18 The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

19. EE141 Arithmetic Circuits 19 Transmission-Gate Full Adder

20. EE141 Arithmetic Circuits 20 Manchester Carry Chain

21. EE141 Arithmetic Circuits 21 Manchester Carry Chain

22. EE141 Arithmetic Circuits 22 Manchester Carry Chain Stick Diagram

23. EE141 Arithmetic Circuits 23 Carry-Bypass Adder Also called Carry-Skip

24. EE141 Arithmetic Circuits 24 Carry-Bypass Adder (cont.) t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum

25. EE141 Arithmetic Circuits 25 Carry Ripple versus Carry Bypass

26. EE141 Arithmetic Circuits 26 Carry-Select Adder

27. EE141 Arithmetic Circuits 27 Carry Select Adder: Critical Path

28. EE141 Arithmetic Circuits 28 Linear Carry Select

29. EE141 Arithmetic Circuits 29 Square Root Carry Select

30. EE141 Arithmetic Circuits 30 Adder Delays - Comparison

31. EE141 Arithmetic Circuits 31 Look-ahead Adder - Basic Idea

32. EE141 Arithmetic Circuits 32 Look-Ahead: Topology Expanding Lookahead equations: All the way:

33. EE141 Arithmetic Circuits 33 Logarithmic Look-Ahead Adder

34. EE141 Arithmetic Circuits 34 Carry Lookahead Trees Can continue building the tree hierarchically.

35. EE141 Arithmetic Circuits 35 Tree Adders 16-bit radix-2 Kogge-Stone tree

36. EE141 Arithmetic Circuits 36 Tree Adders 16-bit radix-4 Kogge-Stone Tree

37. EE141 Arithmetic Circuits 37 Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2

38. EE141 Arithmetic Circuits 38 Tree Adders Brent-Kung Tree

39. EE141 Arithmetic Circuits 39 Example: Domino Adder PropagateGenerate

40. EE141 Arithmetic Circuits 40 Example: Domino Adder PropagateGenerate

41. EE141 Arithmetic Circuits 41 Example: Domino Sum

42. EE141 Arithmetic Circuits 42 Multipliers

43. EE141 Arithmetic Circuits 43 Binary Multiplication Binary Multiplication

44. EE141 Arithmetic Circuits 44 Binary Multiplication Binary Multiplication

45. EE141 Arithmetic Circuits 45 Array Multiplier

46. EE141 Arithmetic Circuits 46 MxN Array Multiplier — Critical Path Critical Path 1 & 2

47. EE141 Arithmetic Circuits 47 Carry-Save Multiplier

48. EE141 Arithmetic Circuits 48 Multiplier Floorplan

49. EE141 Arithmetic Circuits 49 Wallace-Tree Multiplier

50. EE141 Arithmetic Circuits 50 Wallace-Tree Multiplier

51. EE141 Arithmetic Circuits 51 Wallace-Tree Multiplier

52. EE141 Arithmetic Circuits 52 Multipliers —Summary Identify Critical Paths Other Possible techniques: Data Encoding (Booth) Logarithmic v.s. Linear (Wallace Tree Multiplier) Pipelining

53. EE141 Arithmetic Circuits 53 Shifters

54. EE141 Arithmetic Circuits 54 The Binary Shifter

55. EE141 Arithmetic Circuits 55 The Barrel Shifter Area Dominated by Wiring

56. EE141 Arithmetic Circuits 56 4x4 barrel shifter Width barrel ~ 2 p m M

57. EE141 Arithmetic Circuits 57 Logarithmic Shifter

58. EE141 Arithmetic Circuits 58 A 3 A 2 A 1 A 0 Out3 Out2 Out1 Out0 0-7 bit Logarithmic Shifter

59. EE141 Arithmetic Circuits 59 Summary  Datapath designs are fundamentals for high- speed DSP, Multimedia, Communication digital VLSI designs.  Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint.  For details, check “Advanced VLSI” notes, or “Computer Arithmetic”