1. Exploiting Detachability Hashem H. Najaf-abadi Eric Rotenberg

2. Different jobs, Different tools Different applications have different characteristics and therefore different resource needs. Therefore a single fixed architecture compromises the performance of the individual, for the performance of all.

3. Architectural changeability (Transformation) In silicon-based technology; performance of a changeable (polymorphic) design in a fixed configuration is less than a non-changeable implementation of the same configuration.

4. Changeability in subcomponent Changeability at any level of the design hierarchy Changeability in interconnect Sub-component Interconnect Interacting subcomponents may need to change too

5. Changeability at logic-circuit level In an adder for instance; F.A. carry Or the bypasses; F.U.

6. Changeability at the pipeline level In the execution for instance; fetch decode dispatch issue execute write-back execute

7. Changeability at the processor level L2 cache Core A Core B Core C At least there’s no higher level for changeability to spread to.

8. Heterogeneity Pros: No low-level changeability Cons: Poor scalability (die area is consumed, burdening access to system resources) Inflexible (once configurations are placed in the system, they are permanent, while their need is user dependent)

9. Spread Heterogeneity to numerous chips Pros: Increases the overall die area, thus ameliorating the unscalability Cons: Exacerbates the burdening of access to system resources Remains inflexible in the forms of architectural diversity that are made available

10. Exploiting Detachability Detachability: a property that already exists (due to marketing and packaging issues). Pros: No suboptimality due to limited die are or burdening of access to system resources. Flexible in the forms of architectural diversity

11. Exploiting Detachability Other advantages: A substrate for gradual employment of alternate technologies (which tend to be application dependent) A paradigm where architects can focus on innovations for enhancing architectures for specific applications, rather than tweaking the same old design.

12. Changeability in real world applications Rough automatic design-space exploration for the integer SPEC2000 benchmarks Randomly varied the L1 and L2 cache sizes, the processor width, issue queue size, and clock period.

13. Customization results bzipgapgccgzipmcfparserperltwolfvortexvprcrafty No. mem. access cycles345 278323228298328183302 No. front-end cycles13 111291113712 Processor width33335534276 Issue queue size64 16 64 B-to-Back lat. of dep. inst.14 1214912138 Clock period0.1447 0.17970.15470.21870.16760.15220.27180.165 No. L1 access cycles78889108 614 No. L1-cache lines32128641281024512 128 L1-cache line-size163264326432812883264 L1-cache associativity11111141218 No. L2 access cycles13151918553212282016 No. L2-cache lines32643212840961024 5122561024 L2-cache line-size32645122561281632128643216 L2-cache associativity16 8414 8

14. On each other’s bzipgapgccgzipmcfparserperltwolfvortexvprcrafty bzip00.0053*0.01050.00560.10330.10520.21130.20730.04880.11450.1714 gap0.203300.01350.008*0.26840.16150.16230.18630.04750.13520.1105 gcc0.49770.307800.18340.38320.17680.25030.16200.15190.12930.1190 gzip0.21790.06680.0071*00.30.17620.16880.16660.06900.17440.1322 mcf0.51130.47940.52120.453200.50080.59060.35110.53330.38760.3983 parser0.41070.28540.21040.24050.101000.37940.14660.30740.12730.1664 perl0.64600.61410.37510.48220.44910.180200.13470.0035*0.14910.2413 twolf0.46860.33450.20160.24460.09970.0595*0.331100.21830.06650.2472 vortex0.62230.52840.28090.49580.48090.13790.29890.159000.25940.2268 vpr0.43270.25720.16640.25870.11490.03850.25830.0179*0.067700.1803 crafty0.70880.58500.1886 0.62250.33510.18270.35240.0875*0.28370 average 0.429 0.34580.17950.26320.28220.1970.25760.18660.17180.1660.1812 Rows indicate benchmarks, and columns indicate the their customized architectures

15. Representative architectures Assigning surrogates: gcc gzip parser perl twolf vortex vpr crafty gap 7 6 bzip 5 mcf 3 4 2 1

16. Customization results gccmcfparservortexcrafty No. mem. access cycles345278323328302 No. front-end cycles1311121312 Processor width35526 Issue queue size64 B-to-Back lat. of dep. inst.14121413 Clock period0.14470.17970.15470.15220.165 No. L1 access cycles8910 14 No. L1-cache lines641024512128 L1-cache line-size64 32864 L1-cache associativity11128 No. L2 access cycles1955322016 No. L2-cache lines32409610242561024 L2-cache line-size512128166416 L2-cache associativity1641 8