1. Behavior and Software Modeling MPEG Decoder Mapping on Mobile Phone Architecture

2. Mirabilis Design  Confidential2 Model Purpose and Criteria Different methods to model behavior/ software Mapping of behavior on hardware and software Experimentation and analysis Performance, resource utilization and power consumption Compare the performance on the three architectures

3. Mirabilis Design  Confidential3 Top-Level Model Traffic Source Software Definition Computing & Plotting Three Architectures Select Parameters

4. Mirabilis Design  Confidential4 Architecture Parameters Architecture Resources Data Routing Between resources

5. Mirabilis Design  Confidential5 Behavior Modeling: Define instructions an provide latency to Scheduler Behavior Modeling in the uEngine LBL Video_Packet_Loop ; /* Video Packet Loop */ ACT input wait ; /* Wait for DS In */ ACT DS_Out = Input_Queue ; /* Input Queue */ LBL Execute_on_Processor ; /* Schedule Resource */ ACT DS_Out.Task_Time = rand(1000.0, 2000.0) ; /* Execute on Processor */ ACT DS_Out.Cell_Command = Mapping_Name ; /* Send to Mapping Name */ ACT DS_Out.INDEX = Plot_ID ; /* Send to Task ID */ ACT output2 send DS_Out ; /* Send Packet Out */ ACT input2 wait ; /* Wait for Complete */ ACT DS_Out = Input_Queue ; /* Input Queue */ LBL Execute_on_Bus ; /* Schedule Resource */ ACT DS_Out.Task_Time = rand(100.0, 200.0) ; /* Execute on Bus */ ACT Text_ = "B" ; /* Construct Dest */ ACT Text_ += Integer_ ; /* Construct Dest */ ACT DS_Out.Cell_Command = Text_ ; /* Send to Mapping Name */ ACT DS_Out.INDEX = 1 ; /* Send to Task ID */ ACT output2 send DS_Out ; /* Send Packet Out */ ACT input2 wait ; /* Wait for Complete */ ACT DS_Out = Input_Queue ; /* Input Queue */ LBL Execute_on_Cache ; /* Schedule Resource */ ACT DS_Out.Task_Time = rand(100.0, 200.0) ; /* Execute on Cache */ ACT Text_ = "C" ; /* Construct Dest */ ACT Text_ += Integer_ ; /* Construct Dest */ ACT DS_Out.Cell_Command = Text_ ; /* Send to Mapping Name */ ACT DS_Out.INDEX = 2 ; /* Send to Task ID */ ACT output2 send DS_Out ; /* Send Packet Out */ ACT input2 wait ; /* Wait for Complete */ ACT DS_Out = Input_Queue ; /* Input Queue */ LBL Send_Packet_Out ; /* Done with Tasks */ ACT output send DS_Out ; /* Send Packet Out */ Three Sequences Send to Task_Issue

6. Mirabilis Design  Confidential6 Behavior Modeling: Describe pseudo code and latency per task Behavior and Latency Modeling in uEngine LBL Psuedo_Code ; /* SWT adds delay */ ACT Software_Time = irand(1000, 2000) ; /* Convert to Double */ ACT Software_Time *= SWT ; /* Cycle Time */ ACT Software_Time wait ; /* Process Algorithm 1 */ LBL Cycle_Per_Instruction ; SWT JIF Integer_ < 1500 +3 ; /* Follow-On Process */ SWT ACT Integer_ = 1500 - Integer_ ; /* Make a Calc */ SWT GTO +2 ; SWT ACT Integer_ = Integer_ - 1500 ; /* Make a Calc */ SWT WHL Integer_ >= 0 Ext_Code_Execution ; /* While Loop */ SWT ACT Software_Time = SWT * 2.0 ; /* Times 2.0 */ ACT Software_Time wait ; /* Wait for 2 Cycles */ SWT RTN Integer_ -- ; /* End of Loop */ LBL Ext_Code_Execution ; ACT Software_Time = TReal ; /* Wall Clock */ ACT output send DS_Out ; /* Send Packet to SW */ ACT input wait ; /* Wait SW to Finish */ ACT Text2_ = Input_Queue ; /* Input Queue */ ACT Software_Time = TReal - Software_Time ; /* Delta Wall Clock */ ACT Software_Time *= 1.0E-03 ; /* Convert to Seconds */ ACT DS_Out.Task_Time = Software_Time / SW_Cycles_per_Sec ; /* Store in DS */ ACT output2 send DS_Out ; /* Send Packet Out */ GTO Video_Packet_Loop ; /* Repeat */ Latency in DLY Column using a parameter Delay using “wait” statement

7. Mirabilis Design  Confidential7 Software Code Estimation Create a C Wrapper in VisualSim for the decoder code Attached the input and output of the wrapper to the uEngine block Connect output2 of uEngine to a Task_Issue The Real Time difference between the input and output to code is the processing time LBL Video_Packet_Loop ; /* Video Packet Loop */ ACT input2 wait ; /* Wait for DS In */ ACT DS_Out = Input_Queue ; /* Input Queue */ ACT Software_Time = TReal ; /* Wall Clock */ ACT output send DS_Out ; /* Send Packet to SW */ ACT input wait ; /* Wait for SW to Exec */ ACT Text_ = Input_Queue ; /* Input Queue */ ACT Software_Time = TReal - Software_Time ; /* Wall Clock Time */ JIT Software_Time < 1.0 +4 ; /* Fast Software? */ ACT Software_Time *= 1.0E-03 ; /* Convert Msec to Sec */ ACT Software_Time /= SW_Cycles_per_Sec ; /* Convert Cycl to Sec */ ACT DS_Out.Task_Time = Software_Time ; /* Store in DS */ ACT output2 send DS_Out ; /* Send Packet Out */ GTO Video_Packet_Loop ; /* Repeat */ uEngine Software estimation Code

8. Mirabilis Design  Confidential8 Latency and Power Analysis Total Latency for the same operation on different architectures Total Power for the same operation on different architectures

9. Mirabilis Design  Confidential9 Resource Task Graph Activity at each resource on a timeline