1. Computer Organization & Design 计算机组成与设计 Weidong Wang ( 王维东 ) wdwang@zju.edu.cn College of Information Science & Electronic Engineering 信息与通信工程研究所 Zhejiang University

2. Course Information Instructor: Weidong WANG –Email: wdwang@zju.edu.cnwdwang@zju.edu.cn –Tel(O): 0571-87953170; –Office Hours: TBD, Yuquan Campus, Xindian (High-Tech) Building 306, /email whenever TA: –mobile ， Email: »Lu Huang 黄露, 13516719473/6719473; eliver8801@zju.edu.cn »Hanqi Shen 沈翰祺, 15067115046; 542886864@qq.com542886864@qq.com »Office Hours: Wednesday & Saturday 14:00-16:30 PM. »Xindian (High-Tech) Building 308. （也可以短信邮件联系） 2

3. Lecture 14 I/O Design & Bus 3

4. Input/Output

5. ----Input/Output 5

6. Diversity 多样性 of Devices 6

7. Typical x86 PC I/O System 7

8. But the Picture is Somewhat Different Now 8

9. Somewhat Different Now 9

11. I/O System Design Goals 11 Performance measures –Latency (response time) –Throughput (bandwidth) Dependability 可靠性 is important –Resilience in the face of failures –Particularly for storage devices Expandability Computer classes –Desktop: response time and diversity of devices –Server: throughput, expandability, failure resilience –Embedded: cost and response time

12. Throughput 吞吐量 vs. Response Time 12 Throughput –Aggregate 总计的 measure of amount of data moved per unit time, averaged over a window Measure in bytes/sec or transfers/sec –Sometimes referred to as bandwidth Examples: Memory bandwidth, disk bandwidth Response time –Response time to do a single I/O operation Measured in seconds or cycles –Sometimes referred to as latency 延迟 Example: Write a block of bytes to disk Example: Send a data packet over the network

13. Throughput - Response Time Tradeoffs 13

14. Throughput vs. Response Time 14

15. ----Magnetic Hard Disks 15 长效

16. Disk Storage 16 柱 ; 柱面 扇区 磁道

17. Hard Disk 17 硬式的 Basic operation –Rotating platter coated with magnetic surface –Moving read/write head used to access the disk Features of hard disks –Platters are rigid (ceramic or metal) –High density since head can be controlled more precisely –High data rate with higher rotational speed –Can include multiple platters Incredible improvements –Examples of I/O device performance being technology driven –Capacity: 2x every year –Transfer rate: 1.4x every year –Price approaching 1$/GB = 10 9 bytes

18. Hard Disk Organization 18 转盘 柱 ; 柱面

19. Measuring Disk Access Time 19 Each read or write has three major components –Seek time is the time to position the arm over the proper track –Rotational latency is the wait for the desired sector to rotate under the read/write head –Transfer time is the time required to transfer a block of bits (sector) under the read/write head Note that these represent only the “raw performance” of the disk –Other components: I/O bus, controllers, other caches, interleaving, etc.

20. Seek Time 20 Seek time is the time to position the arm over the proper track Average seek time is the time it takes to move the read/write head from its current position to a track on the disk Industry definition is that seek time is the time for all possible seeks divided by the number of possible seeks –In practice, locality reduces this to 25-33% of this number –Note that some manufacturers report minimum seek times rather average seek times

21. Rotational Latency 21

22. Transfer Time 22 Transfer time is the time required to transfer a block of bits A factor of the transfer size, rotational speed, and recording density –Transfer size is usually a sector Most drives today use caches to help buffer the effects of seek time and rotational latency

23. Typical Hard Disk Drive 23 Typical hard disk drive –Rotation speed: 3600,5200,7200, or 15000 RPM –Tracks per surface: 500-2000 tracks –Sectors per track: 32-128 sectors –Sectors size: 512B-1024KB –Minimum seek time is often approximately 0.1ms –Average seek time is often approximately 5-10ms –Access time is often approximately 9-10ms –Transfer rate is often 50-200MB/s

24. Average Access Example 24

25. Important Footnote 25

26. Dependability 可靠性 26 背离

27. Dependability 可靠性 Measures 27 Reliability 可靠 : mean time to failure (MTTF) Service interruption: mean time to repair (MTTR) Mean time between failures –MTBF = MTTF + MTTR 可用性 Availability = MTTF/ (MTTF + MTTR) Improving availability –Increase MTTF: fault avoidance, fault tolerance, fault forecasting –Reduce MTTR: improved tools and processes for diagnosis and repair How would you improve the availability of a storage system? –Assume multiple disk…

28. I/O System Design Example: Transaction Processing 事务处理 28 Examples: Airline reservation, bank ATM, inventory system, e-business –Many small changes to shared data space Each transaction: 2-10 disk I/Os, ~2M=5M CPU instruction per disk I/O –Demands placed on system by many different users Important Considerations 注意事项 –Both throughput and response times are important High throughput needed to keep cost low (transactions/sec) Low response time is also very important for the users –Terrible locality –Requires graceful 得体的 handling of failures Redundant storage & multiphase operations

29. I/O Performance Factors 29 Overall performance is dependent upon a many factors –CPU How fast can the processor operate on the data? –Memory system bandwidth and latency Multilevel caches Main memory –System interconnection I/O and memory buses I/O controllers –I/O devices (disks) –Software efficiency I/O device handler instruction path length, OS overhead, etc

30. I/O System Design 30

31. Typical Storage Design Problem 31 业务

32. Solution Part1: pick a disk 32 承受

33. Solution Part2: pick CPU configuration 33

34. Buses 34

35. Review: Typical x86 PC I/O System 35

36. Buses A bus sharedcommunication linkA bus is a shared communication link that connects multiple devices Single set of wires connects multiple “subsystems” as opposed to a point to point link which only two components together Wires connect in parallel, so 32 bit bus has 32 wires of data

37. Advantages –Broadcast capability of shared communication link –Versatility New device can be added easily Peripherals can be moved between computer systems that use the same bus standard –Low Cost A single set of wires is shared multiple ways Disadvantages –Communication bottleneck Bandwidth of bus can limit the maximum I/O throughput –Limited maximum bus speed Length of the bus Number of devices on the bus Need to support a range of devices with varying latencies and transfer rates Advantages/Disadvantages 37 多样性, 多功能

38. Bus Organization 38

39. Types of Buses Processor-memory bus or front-side bus or system bus –Short, high-speed bus –Connects memory and processor directly –Designed to match the memory system and achieve the maximum memory-to-processor bandwidth (cache transfers) –Designed specifically for a given processor/memory system (proprietary) I/O Bus (or peripheral bus) –Usually long and slow –Connect devices to the processor-memory bus –Must match a wide range of I/O device performance characteristics –Industry standard

40. Review: Typical x86 PC I/O System 40

41. Synchronous versus Asynchronous 41 Synchronous Bus –Includes a clock in control lines –Fixed protocol for communication relative to the clock –Advantages Involves very little logic and can therefore run very fast –Disadvantages Every decision on the bus must run at the same clock rate To avoid clock skew, bus cannot be long if it is fast –Processor-memory bus Asynchronous Bus –No clock control line –Can easily accommodate a wide range of devices –No clock skew problems, so bus can be quite long –Requires handshaking protocol

42. Increasing Bus Bandwidth 42

43. Increasing Bus Bandwidth 43

44. Increasing Bus Bandwidth 44

45. Accessing the Bus 45

46. Multiple Masters 46 With multiple masters, arbitration must be used so that only one device is granted access to the bus at a given time Arbitration 仲裁 –The bus master wanting to use the bus asserts a bus request –The bus master cannot use the bus until the request is granted –The bus master must signal the arbiter when finished using the bus Bus arbitration goals –Bus priority – highest priority device should be serviced first –Fairness 公平 – Lowest priority devices should not starve 饿死

47. Centralized Parallel Arbitration 47

48. Case Study: PCI- 周边元件扩展接口 48

49. 32 bit PCI Signals 49

50. PCI Read 50

51. PCI Read Steps 1 51

52. PCI Read Steps 2 52

53. Trends for Buses Logical Bus and Physical Switch 53

54. PCI vs. PCI Express 54

55. Operating System Tasks 55

56. OS Communication 56 The operating system should prevent user program from communicating with I/O device directly –Must protect I/O resources to keep sharing fair –Protection of shared I/O resources cannot be provided if user programs could perform I/O directly Three types of communication are required –OS must be able to give commands to I/O devices –I/O device must be able to notify OS when I/O device has completed and operation or has encountered an error –Data must be transferred between memory and an I/O device

57. I/O Commands: A method for addressing a device 57

58. I/O Commands 58 I/O devices are managed by I/O controller hardware –Transfers data to/from device –Synchronizes operation with software Command registers –Cause device to do something Status registers –Indicate what the device is doing and occurrence of errors Data registers –Write: transfer data to a device –Read: transfer data from a device

59. Communication with the CPU 59 Method #1: Polling 轮询 –I/O device places information in a status register –The OS periodically checks the status register –Whether polling is used dependent upon whether the device can initiate I/O independently For instance, a mouse works well since it has a fixed I/O rate and initiates its own data (whenever it is moved) For others, such as disk access, I/O only occurs under the control of the OS, so we poll only when the OS knows it is active –Advantages Simple to implement Processor is in control and does the work –Disadvantage Polling overhead and data transfer consume CPU time

60. Polling and Programmed I/O 60

61. I/O Notification 61

62. I/O Interrupts 62 中断向量 中断服务程序

63. Data transfer 63 North Bridge 北桥

64. Delegating 授权委派 I/O: DMA 64 Direct Memory Access (DMA) –Transfer blocks of data to or from memory without CPU intervention –Communication coordinated by the DMA controller DMA controllers are integrated in memory or I/O controller chips –DMA controller acts as a bus master, in bus-based systems DMA steps –Processor sets up DMA by supplying Identify 识别确定 of the device and the operation (read/write) The memory address for source/destination The number of bytes to transfer –DMA controller starts the operation by arbitrating 仲裁 for the bus and then starting the transfer when the data is ready –Notify the processor when the DMA transfer is complete or on error Usually using an interrupt

65. Reading a Disk Sector (1) 65

66. Reading a Disk Sector (2) 66

67. Reading a Disk Sector (3) 67

68. DMA Problems: DMA Problems: Virtual vs. Physical Addresses 68 If DMA uses physical addresses –Memory access across physical page boundaries may not correspond to contiguous 邻近的 virtual pages (or even the same application) Solution1: <1 page per DMA transfer Solution1+: chain a series of 1-page requests provided by the OS –Single interrupt at the end of the last DMA request in the chain Solution2: DMA engine uses virtual addresses –Multi-page DMA requests are now easy –A TLB is necessary for the DMA engine For DMA with physical addresses: pages must be pinned in DRAM 用针别住 / 钉在 –OS should not page to disks pages involved with pending 挂起的 I/O

69. DMA Problems DMA Problems: Cache Coherence 69 A copy of the data involved in a DMA transfer may reside in processor cache –If memory is updated: must update or invalidate 使作废 “old” cache copy –If memory is read: must read latest value, which may be in the cache Only a problem with write-back caches This is called the “cache coherence” problem –Same problem in multiprocessor systems

70. DMA & Coherence 一致性 70 Solution 1: OS flushes 冲刷 the cache before I/O reads or forces write backs before I/O writes –Flush/write-back may involve selective addresses or whole cache –Can be done in software or with hardware (ISA) support Solution 2: Route memory accesses for I/O through the cache –Search the cache for copies and invalidate or write-back as needed –This hardware solution may impact performance negatively 消极地 While searching cache for I/O requests, it is not available to processor –Multi-level, inclusive 包容性 caches make this easier Processor searches L1 cache mostly (until it misses) I/O requests search L2 cache mostly *until it finds a copy of interest)

71. I/O: Bus & Software Issues 71

72. Review: Hard Disks 72

73. Flash Storage 73

74. Flash Types 74

75. Another Example: Rack-Mounted Servers 75

76. Sun Fire x4150 1U server 76

77. I/O System Design Example 77

78. Design Example 78

79. Design Example (cont) 79 充足的净空高度

80. I/O Summary 80 I/O performance has to take into account many variables –Response time and throughput –CPU, memory, bus, I/O device –Workload e.g. transaction processing I/O devices also span a wide spectrum –Disks, graphics, and networks Buses –Bandwidth –Synchronization –Transactions OS and I/O –Communication: Polling 轮询 and Interrupts –Handling I/O outside CPU: DMA

81. HomeWork Readings: –Read Book; –Read Parallel Processors from Client to Cloud.pdf; HW10 (-5th) –Project 2 –Computer Organization and Design (COD) » (Fifth Edition) 81

82. Acknowledgements These slides contain material from courses: –UCB CS152 –Stanford EE108B –Also MIT course 6.823 82