2. Flip-Flop

3. Flip-flops Objectives Upon completion of this chapter, you will be able to :  Construct and analyze the operation of a latch flip-flop made from NAND or NOR gates  Identify and understand the operation of RS, JK, D, T flip- flops  Understand edge-triggered flip-flops  Describe the difference between synchronous and asynchronous systems

4. Introduction  Flip-flop is digital circuit which functions as a memory element used in the digital system.  Flip-Flop is made up of an assembly of logic gates. Even though a logic gate, by itself, has no storage capability.  Flip-Flop is also known as latch and bi-stable multi-vibrator.

5. General Flip-flop Symbol The symbol shows two outputs, labeled Q and Q, that are the inverse of each other The FF can has one or more inputs. These inputs are used to cause the FF to switch back and forth between its possible output states QQQQ FF inputs outputs

6. General Flip-flop Symbol Flip-Flop has two allowed output states. SET state :- where Q = 1and Q = 0. RESET state :- where Q = 0 and Q = 1. QQQQ FF inputs outputs Thus, flip-flop is also known as bi-stable multi-vibrator or latch.

7. Various type of Flip-Flops RSRS QQQQ R S J K D D T QQQQ T > QQQQ QQQQ JKJK > Clk Tutorial

8. RS Flip-Flops The most basic flip-flop is RS flip-flop. The inputs are labeled as SET ( S ) and RESET ( R ). The RS flip-flop can be constructed from logic gates. QQQQ FF outputs SRSR inputs

10. RS Flip-Flops NAND-1 NAND-2 SRSR QQQQ NAND gate FF is an active low FF. A logic 0 activates set S i.e. S = 0 Q = 1 0 1 To reset the FF, apply a logic 0 to R i.e. R = 0 Q = 1 0 1 Click TO Continue NAND gate FF

11. RS Flip-Flops NAND-1 NAND-2 SRSR QQQQ Truth table for NAND gate RS FF S R Q Q Remarks Click TO Continue NAND gate FF 0 0 1 1Prohibited state 0 1 0 1 1 0 Set state, Q =1 0 1 1 0 1 0 0 1 Reset state, Q =1 1 0 0 1 1 1 0 1 Unchanged / Hold 1 0 0 1

12. RS Flip-Flops Block logic symbol for RS FF using NAND gate can be as in Fig A QQQQ FF outputs SRSR inputs or Fig B. Fig A QQQQ FF outputs SRSR inputs Fig B Click TO Continue NAND gate FF

13. RS Flip-Flops Timing diagrams Click TO Continue NAND gate FF QQQQ FF SRSR Q SRSR T 0 T 1 T 2 T 3 T 4 At time :- T 0 :- FF is at reset state; i.e. Q=0. T 1 :- reset signal will reset the FF. T 2 :- set signal will set the FF. T 3 :- set signal will set the FF. T 4 :- reset signal will reset the FF.

14. RS Flip-Flops NOR gate FF The two NOR gates are cross - coupled so that the output of NOR-1 is connected to one of the inputs of NOR-2, and vice versa. NOR -1 NOR -2 SRSR QQQQ

15. RS Flip-Flops NOR gate FF is an active HIGH FF. A logic 1 activates set S i.e. S = 1 Q = 1 To reset the FF, apply a logic 1 to R i.e. R = 1 Q = 1 NOR gate FF NOR -1 NOR -2 SRSR QQQQ Click TO Continue

16. RS Flip-Flops NAND-1 NAND-2 SRSR QQQQ Truth table for NOR gate RS FF. S R Q Q Remarks NOR gate FF 1 1 Prohibited state 1 1 0 Set state, Q =1 0 1 0 1 Reset state, Q =1 1 0 0 0 0 1 Unchanged / Hold 0 0 1 Click TO Continue

17. RS Flip-Flops Block logic symbol for RS FF using NOR gate QQQQ FF outputs SRSR inputs NOR gate FF

18. RS Flip-Flops Timing diagrams Click TO Continue NOR gate FF QQQQ FF SRSR Q SRSR T 0 T 1 T 2 T 3 T 4 At time :- T 0 :- FF is at reset state; i.e. Q=0. T 1 :- set signal will set the FF. T 2 :- reset signal will reset the FF. T 3 :- reset signal will reset the FF. T 4 :- set signal will set the FF.

19. RS Flip-Flops Flip-flop operates without clock input is called asynchronously. But most digital systems operate synchronously, that is operate in step with a clock signal. Flip-flop are mostly triggered by clock pulses. Click TO Continue Triggering of FF Clock pulses signal

20. RS Flip-Flops Flip-flop may be positive edge triggered or negative edge edge triggered. Click TO Continue Triggering of FF Clock pulses signal A positive edge-triggered flip-flop transfer data from the input to the output on the leading edge of the clock pulse. A negative edge-triggered flip-flop transfer data from the input to the output on the falling edge of the clock pulse.

21. RS Flip-Flops Symbol of edge triggered flip-flop QQQQ SRSR Clk QQQQ SRSR Positive edge triggered Negative edge triggered

22. RS Flip-Flops QQQQ QQQQ SRSR Clk Positive edge triggered S R Clk Logic circuit of edge triggered FF

23. JK Flip-Flops The J and K inputs are the data inputs, and clock input transfers data from inputs of the flip-flop to the outputs in the same ways as RS flip- flop. The advantage of JK flip-flop is that it does not have the problem of a prohibited input combinations found in RS flip-flop. Symbol of positive edge-triggered JK FF QQQQ J CLK K

24. JK Flip-Flops Symbol of positive edge-triggered JK FF Truth table Toggle mode means when both JK are left high the FF will change states for each clock pulse. QQQQ J CLK K

25. JK Flip-Flops QQQQ J CLK K J K Clk Q All inputs are 0, and Q = 1J=0, K=1, Clk = and Q = 0 J=1, K=1, Clk = and Q toggles to 1 J=0, K=0, Clk = and Q remain at 0 J=1, K=1, Clk = and Q toggles to 1 Waveform diagram for a JK flip-flop Click TO Continue

26. JK Flip-Flops For the clocked flip-flops, the J,K, R, and S inputs have been referred to as control inputs. These inputs are called synchronous input, because their effect on the FF output is synchronized with the CLK input. QQQQ J CLK K

27. JK Flip-Flops Asynchronous inputs operate independently of the synchronous inputs and clock input. These inputs can be used to set the FF to the 1 state or clear the FF to the 0 state at any time, regardless of the conditions at the other inputs. QQQQ J CLK K PR CLR Asynchronous inputs

28. JK Flip-Flops Figure show J K FF has two asynchronous inputs PR and CLR. These are active-Low inputs as indicated by the bubbles on the FF symbol. When PR = CLR=1, the asynchronous inputs are inactive. QQQQ J CLK K PR CLR Asynchronous inputs

29. JK Flip-Flops When PR = CLR = 1, the asynchronous inputs are inactive. PR = 0, and CLR = 1, Q = 1 CLR = 0 and PR = 1, Q = 0 PR = CLR = 0, this condition should not be used ( prohibited ), as it can result in an ambiguous response. QQQQ J CLK K PR CLR Asynchronous inputs

30. D Flip-Flops The D flip-flop is also called Delay or Data flip-flop. The D flip-flop has only one input. It can be easily implemented from the RS or JK inputs as shown. QQQQ SRSR D QQQQ JKJK D

31. D Flip-Flops Edge-triggered D FF Truth table Q follows D on the rising edge of the clock pulse. QQQQ D CLK D Clk Q 0 1 X 0 no change “ X ” indicates “don’t care” Click TO Continue

32. D Flip-Flops D Clk Q Initially Q = 1 D =1, Clk = and Q = 1 Waveform diagram for a D flip-flop Click TO Continue QQQQ D CLK D = 0, Clk = and Q = 0 D = 1, Clk = and Q = 1

33. D Flip-Flops Level-triggered D FF Truth table Q follows D when the FF is enabled; i.e. when EN = 1 QQQQ D EN D EN Q X 0 no change 1 1 1 0 1 0

34. D Flip-Flops Waveform diagram for a D flip-flop Click TO Continue QQQQ D EN D EN Q Both D and EN inputs are 0, and Q = 0 D =1, EN = 0 and Q = 0 D =1, EN = 1 and Q = 1 D =0, EN = 1 and Q = 0 D = 1, EN = 1 and Q = 1 D = 0, EN = 0 and Q = 1 “Latched”“Transparent”

35. T Flip-Flops The T flip-flop is also called toggle flip-flop. QQQQ JTKJTK QQQQ T QQQQ JTKJTK QQQQ J CLK K High It can be easily implemented by tying the JK inputs of the JK FF to high as shown.

36. T Flip-Flops QQQQ T Truth table Q n Clk Q n+1 1 0 1 0 0 1

37. T Flip-Flops QQQQ T Wave format T input Wave format Q output f o = 1/2 f in f o : Output frequency at Q f in : Input frequency at T

38. When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at B) Reset state. C) Hold state. D) Prohibited state. QQQQ FF SRSR Q 1 A) Set state.

39. The flip-flop shown can be constructed by using B) OR gates C) NAND gates D) NOR gates QQQQ FF SRSR Q 2 A) AND gates

40. The following symbol shows B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. Q 3 QQQQ FF SRSR A) An active high RS Flip-flop.

41. A negative-edge-triggered flip-flop transfers data from input to output on the B) leading edge of the clock pulse C) positive level of the clock pulse. D) zero level of the clock pulse. Q 4 A) falling edge of the clock pulse

42. JK flip-flop does not result in A) set state B) hold state C) toggle state D) prohibited state Q 5

43. When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level. Q 6 A) reset the Q output.

44. Which of the following sequence will reset the flip-flop? B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. Q 7 QQQQ J CLK K PR CLR A) J=K=1, PR=CLR=1, and CLK =

45. Which of the following JK flip-flop’s mode is not an asynchronous operation? B) Clear C) Toggle D) Hold Q 8 A) Set

46. Refer to the figure shown; a clocked RS flip-flop had been converted to B) D latch C) T flip-flop D) JK flip-flop Q 9 QQQQ S CLK R A) D flip-flop

47. Refer to the figure shown; for CLK frequency = 20 kHz the output frequency is B) 10 kHz C) 20 kHz D) 40 kHz Q 10 QQQQ D CLK A) 0 Hz

48. When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at A) Set state. B) Reset state. C) Hold state. D) Prohibited state. QQQQ FF SRSR Q 1 Output Remain unchanged. Wrong !

49. When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at A) Set state. B) Reset state. C) unchanged state. D) prohibited state. QQQQ FF SRSR Q 1 NOR gate FF would not response to logic ‘0’ Solution

50. The flip-flop shown can be constructed by using B) OR gates C) NAND gates D) NOR gates QQQQ FF SRSR Q 2 A) AND gates Wrong ! Hints! Look for active low gates.

51. The flip-flop shown can be constructed by using A) AND gates B) OR gates C) NAND gates D) NOR gates QQQQ FF SRSR Q 2 NAND gate FF is an active low FF. Solution

52. The following symbol shows A) An active high RS Flip- flop. flop B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. QQQQ FF SRSR Q 3 Wrong ! Hints, Its an edge-triggered FF

53. The following symbol shows A) An active high RS Flip- flop. flop B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. QQQQ FF SRSR Q 3 Wrong ! Hints, Bubble represents negative !

54. The following symbol shows A) An active high RS Flip- flop. flop B) An active low RS Flip-flop. C) An positive edge-trigger active low RS Flip-flop. D) An negative edge-trigger active low RS Flip-flop. Q 3 A bubble at the clock input represent an negative edge-trigger FF. Solution QQQQ FF SRSR

55. A negative-edge-triggered flip-flop transfers data from input to output on the A) falling edge of the clock pulse B) leading edge of the clock pulse C) positive level of the clock pulse. D) zero level of the clock pulse. Q 4 Negative edge-trigger also referred to falling edge- trigger FF. Solution

56. JK flip-flop does not result in A) set state B) hold state C) toggle state D) prohibited state Q 5 Prohibited state only happened in RS FF Solution

57. When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level. Q 6 When J=0,K=1 Q output will be reset. A) reset the Q output. Wrong !

58. When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level. Q 6 When J=1,K=0 Q output will be set. A) reset the Q output. Wrong !

59. When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level. Q 6 When J=K=0 Q output will be hold. A) reset the Q output. Wrong !

60. When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to B) set the Q output. C) hold the Q output. D) toggle the Q output to the next logic level. Q 6 When both JK FF inputs are at logic 1, the FF is said to be operated in toggle state. A) reset the Q output. Solution

61. Which of the following sequence will reset the flip-flop? B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. Q 7 QQQQ J CLK K PR CLR Hints! PR and CLR are asynchronous inputs. A) J=K=1, PR=CLR=1, and CLK = Wrong !

62. Which of the following sequence will reset the flip-flop? B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. Q 7 QQQQ J CLK K PR CLR Good try! Take notes of the bubble. A) J=K=1, PR=CLR=1, and CLK = Wrong !

63. Which of the following sequence will reset the flip-flop? B) J=K=0, PR=CLR=1, and CLK= C) J, K, and CLK = X, where PR = 1 and CLR = 0. D) J, K, and CLk = X, where PR = 0 and CLR =1. Q 7 QQQQ J CLK K PR CLR PR and CLR are asynchronous inputs, CLR=0 will reset the FF. A) J=K=1, PR=CLR=1, and CLK = Solution

64. Which of the following JK flip-flop’s mode is not an asynchronous operation? B) Clear C) Toggle D) Hold Q 8 Toggle operation only took place when the Ff is triggered. A) Set

65. Refer to the figure shown; a clocked RS flip-flop had been converted to B) D latch C) T flip-flop D) JK flip-flop Q 9 QQQQ S CLK R By connecting an inverter between the RS inputs of the FF, a D FF is formed. A) D flip-flop

66. Refer to the figure shown; for CLK frequency = 20 kHz the output frequency is B) 10 kHz C) 20 kHz D) 40 kHz Q 10 QQQQ D CLK D FF was wired as an frequency divider cct., the output frequency = ½ clock frequency. A) 0 Hz