1. High Speed Digital System Lab Spring 2009 1 semester project  Instructor: Mony Orbach  Students: Pavel Shpilberg Ohad Fundoianu

2.  Introduction  Project targets  Block diagram  Stratix 2 transmitter  Stratix 2 reciever  Work environment  Changeable parameters  Time table

3.  As technology have gotten faster, the demand for higher data transfer rates between devices has grown.  It turns out that the serial communication provides better solution, than the parallel one.  A known serial high speed communication protocol is PCI-Express.

4.  Implementation of high speed digital channel  Examining Stratix card ability of GX (protocols and parameters).  Testing the channel by checking the distortion of signals along the lines.  Learning and understanding the physical part of high speed channels.

5. Serilizer Encoding PLL Channel: rate: up to 6.375 Gbps DeserilizerDecoding

6. Phase compensation Byte serializer * 8B/10B Encoder * Serializer PLL

7. Word Aligner Deserializer PLL+CRU Byte Deserializer * 8B/10B Decoder * Rate matcher * Phase compensation

8.  The channel will be implemented using Stratix 2 GX card. Working tools: 1) Quartus 2 – Design and programming in VHDL. 2) Hyperlinx – Simulation of transmissions lines.

9.  Serial channel rate: 600[Mbps]-6.375[Gbps]  PLL ref. clock rates 50-622.08[MHz]  Varies types of functional modes : PCIE, SONET/SDH, GIGE, Basic, XAUI.  Receiver termination (100,120,150)  Pre-emphasis and equalization  8B/10B coding  Rate matcher  Byte deserializer

10. 9/416/423/430/47/514/521/5 Characterization presentationCharacterization presentation Stratix 2 GX acquaintanceStratix 2 GX acquaintance Understanding programmable parameters. Learning Quartos work environment. Learning physical attributions of HS channels. Start implementing the HS channel.