1. Status of Clermont-Ferrand R&D works Tiles session in AUW François Vazeille LPC Clermont-Ferrand ● Mechanics ● External High Voltage Power Supply ● Active Dividers ● Very Front End/Front End readout ● Summary 1

2. Slider 3 More Girder Rings Increased gap by 1-2/10 mm ● New Slider and new Basket  Improvements made as proposed in Tilecal meeting (CERN, 4 July 2013) - Easiest insertion/extraction. - Contacts with more Girder Rings. Mechanics Larger radius of the round shape 2

3. Basket 2 ▪ More space for connection operations. ▪ Simultaneous access to several PMT Blocks. Comments: -As discussed with Ferran, these Baskets will be not used every time. - They offer the advantage of removing any effort on the Girder Rings when the Mini-Drawers are inserted (because of their fixation on the Finger). 3 + space for the plastic positionning tool of PMT Block.

4. Guiding up to the entrance The "perfect" alignment of the Slider and Basket 4

5. ● Next actions - New tests in Building 175 using the Turning Block + Tilecal module with Finger Proposed date: November 26-27. - Use of this Slider 3 for the first Demonstrator tests, after modifications if needed. - Study of new types of Baskets: ▪ Baskets in Two half-pieces  Transport and easy dismounting (restricted room). ▪ Super-Basket able to welcome a Super-Drawer (made of 4 Mini-Drawers)  In-situ electronics tests … if enough space. - The Clermont-Fd activities on Mechanics will be centered on the handling tools. 5

6. External High Voltage ● Preliminary tests at LPC  Noise problems at low (50 Hz) and high frequency (100-200 KHz) now identified:  LV power supplies located inside the regulation crate (see next slide). They are switching power supplies.  Types of HV Source.  Location in the room (50 Hz not everywhere !). ● More systematic tests foreseen at LPC with LV power supplies outside the regulation crate, and different set-ups (Direct HV noise measures, PMT/LED noise measures). 6

7. Regulation crate HV Source DCS Multiconductor cables - 1m. - 4 x 20 m long (175) - 100 m (ATLAS) LV Source 7 LV Source inside the crate.

8. ● Next actions - Tests in the building 175: proposed date November 26-27.  Noise comparisons CERN/LPC without needs of a Tilecal module. - Later: new tests in 175 using Mini-Drawers. - Information on the cable routing and about the Patch-Panel for Barcelona: sizes will be given. 8 Connector covers not mounted here.

9. Active Dividers ● New radiation rules … not yet fully official  Discussion with Philippe Farthouat and the Report of the Radiation Estimate Task-Force F. Lanni on behalf of the Radiation Estimate Task-Force (RETF)  roughly 40% of previous rules. RadiationsSimulation factor Max radiation for Dividers NIEL (Neutrons) 1 MeV eq.n/cm 2 51.5 10 13 20.6 10 13 TID (Gammas) Grays 3.5525 1.5225  New Proposed strategy: testing up to the previous values, taking benefit from the on-line monitoring to cross the new values. 9

10. ● NIEL radiation tests made at VALDUC (CEA) (September 9-10) PROSPERO reactor  roughly 10 9 neutrons/cm 2 /s during 4 h. - Full application of the ATLAS rules 3 Last stages: 20 pieces 16 Transistors 8 Diodes - Irradiated PCB up to 1.5 10 13 1 MeV eq.n/cm 2. + Associated electronics for the on-line monitoring. - Preliminary results (Waiting for PROSPERO calibrations)  True effects of neutrons: gain losses of transistors.  Simulations using the final Gain values  non-linearity always < Passive Dividers (not sensitive to radiations).  Will be better using the new radiation levels - Final results at the next upgrade meeting. 10

11. ● TID radiation tests: foreseen at Argonne with our bench - Waiting for the 30 m long cables connecting the irradiated PCB, but not yet back from VALDUC. - We propose to make new cables then to give everything to Argonne. Comment: we will provide written explanations, but it will be better to meet somebody for a small learning. ● Tilecal Divider Note in stand by, waiting for noise measurements as proposed by readers  Very low level makes difficult these measures/frequency, but we go on. ●Active Divider production status  Defaults on a large part of the 350 manufactured Dividers □ 80% rejected at the first delivery (HV cable welding). □ New delivery (with new cables): other defaults !  Repairs … at LPC, then certification on the Test Bench (100 Dividers delivered at CERN before August). 11

12. VFE/FE readout ● General scheme of TACTIC1 -12 bits ADC working at 40 MHz. -IBM CMOS 130 nm technology. -Pipeline architecture with 2 bits/stage using a 1.5 bit/stage algorithm and a gain of 2 on each stage amplifier. TACTIC1 (1.8 x 1.8 mm 2 ) 12

13. -Noise < 1 LSB  Specifications OK. -Power consumption: 61 mW (Measured and simulated). -Bad Integral Non Linearity ▪ Blue: measures. ▪ Red: Simulation with 1.5 bit/stage algorithm + degrading the gain of the various stages from 2.0 to about 1.99 -Explanation: bad coupling of amplifier capacitors plus parasitic effects. -Off-line analysis to recover linearity  ADC ENOB ~ 11 bits (Simulations gave 10.81 bits). ● Full tests of TACTIC1 The ADCs work 13 Test bench Measured noise of 0.83 LSB

14. ● Next steps - Spring 2004: Simple Demonstrator using FATALIC3 + 1 TACTIC1 only. + Making of the 3in1 card + Main Board (1 Daughter Board needed !). - Full simulations of TACTI2: ▪ Smaller surface (an a lower consumption). ▪ Correction of defaults  To improve Precision and Linearity. - Full simulation of the complete lay-out of FATALIC4, including 3 TACTIC2.  Foundry by May 2014 for a delivery in November. - Evolutions of 3in1 card and Main Board.  A very challenging program with important manpower from Micro-electronics service (To take all the requested time on simulations) and Electronics service (Environment of chips and tests) + Physicists for off-line studies. - New Integrator tests of FATALIC 3 with Cesium at CERN < Xmas 2013. 14

15. SUMMARY R&DProspective et échéances Active Dividers -TID at Argonne < end 2013 if possible. -Final analysis of NIEL at LPC < end 2013. -Writing of 2 Notes (Certification, Radiations) < end 2013. - R&D completed end 2013. External High Voltages -Full understanding of noise sources. -Tests at LPC, then CERN (175), then ATLAS 2015. -R&D completed spring 2014 ? Mechanics Mini- Drawers -R&D completed at LPC  Go on at Barcelona and Bucharest. -Writing of a Note. Tools -New tests at CERN on November 26-27. -Used by other Institutes in 2014. -Small LPC activity in 2014 for evolutions. VFE/FE VFE: FATALIC/ TACTIC -New digital integrator tests with FATALIC3 < end 2013 ? -Decisions on "Peaking time" and "Shaping" < end 2013 ? -Simple test FATALIC3 + 1 TACTIC1 by Spring 2013. -Deep simulations of TACTIC2 and FATALIC4. -Foundry of FATALIC4 with TACTIC2 in May 2014. -Delivery/tests of FATALIC4 on November 2014. FE: 3in1 and MB 2 -First versions Spring 2014. -Evolutions for FATALIC4 on November 2014. VFE/FE will become the main activity 15