1. Microfabrication Home exercise #3 Return by Feb 21st, 22 o’clock Sasha.hoshian@aalto.fi

2. Q1: JFET fabrication process Explain step-by-step the fabrication process of the JFET shown below. Assuming source to have 2 µm linewidth, explain other sizes and spacings. Also list junction depths and film thicknesses. Hint: gate/source metallization is done in the end. n+ substrate n- epi p+ n+ p+ drain gate source gate

3. Q2: Passives What is the nitride thickness if areal capacitance density is 4 nF/mm 2, and nitride  =7 ? Why is the capacitor bottom contact hole made by plasma etching and top contact hole by wet etching ? SiCr thin film resistor resistivity is 2000 µOhm-cm. Design a 5 kOhm resistor ! How much area is needed if 3 µm LW is used ? SiCr resistor

4. Q3: Capacitor design (2 points) a)Explain step-by-step the fabrication process of the bonded capacitor. Both top and bottom plates are aluminum, and dielectric is air. b) If C=4 pF is needed, give dimensions of the device! c) If 1 fF capacitance change is detectable, what is the corresponding displacement of the movable electrode ? Pyrex Al

5. Q4. Thermal oxidation a) Explain where thermal oxide will grow in the structure shown on the right. Very detailed answer, by drawing ! b) What else will happen during thermal oxidation ?

6. Q5. Ion implantation a) If 200 mm wafers receive 10 15 cm -2 phosphorous implant dose, how many wafers can be implanted using a PH 3 bottle of 3 liter volume (STP) ? b) If ion current is 1mA, what is the interval for bottle changing ?