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2. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami2 Figure 11.1 Multiplication of 4-bit numbers in dot notation.

3. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami3 Figure 11.2 Step-by-step multiplication examples for 4-digit unsigned binary and decimal numbers.

4. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami4 Figure 11.3 Step-by-step multiplication examples for 4-digit 2’s-complement numbers.

5. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami5 Figure 11.4 Hardware multiplier based on the shift-add algorithm.

6. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami6 Figure 11.5 Shifting incorporated in the connections to the partial product register rather than as a separate phase.

7. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami7 Figure 11.6 Schematic diagrams for full-tree and partial-tree multipliers.

8. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami8 Figure 11.7 Array multiplier for 4-bit unsigned operands.

9. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami9 Figure 11.8 Register usage for programmed multiplication superimposed on the block diagram for a hardware multiplier.

10. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami10 Figure 11.9 Division of an 8-bit number by a 4-bit number in dot notation.

11. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami11 Figure 11.10 Step-by-step division examples for 8/4-digit unsigned binary integers and decimal fractional numbers.

12. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami12 Figure 11.11 Step-by-step division examples for 4/4-digit unsigned binary integers and fractional numbers.

13. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami13

14. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami14 Figure 11.12 Hardware divider based on the shift-subtract algorithm

15. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami15 Figure 11.13 Shifting incorporated in the connections to the partial remainder register rather than as a separate phase.

16. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami16 Figure 11.14 Array divider for 8/4-bit unsigned integers.

17. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami17 Figure 11.15 Register usage for programmed division superimposed on the block diagram for a hardware divider.