1. 1 of 24 The new way for FPGA & ASIC development © 2004-2008 GE-Research

2. Semulator V2.4dsr2 of 16 Development of complex FPGA and ASIC Stable parts transferred to Hpe_midi Design File VHDL Design File Verilog Testbench Files HDL Simulator and Hpe Desk Design File SystemC Design FilesMacro3Macro4Macro1Macro2 Simulation & Emulation Stable parts transferred to Hpe_midi SEmulation = Simulator controlled Emulation Hpe_midi R a p i d P r o t o t y p i n g S y s t e m H D L S i m u l a t o r

3. Semulator V2.4dsr3 of 16 Development of complex FPGA and ASIC Testbench Files HDL Simulator and Hpe Desk Macro3Macro4 Hpe_midi Design File VHDL Macro1Macro2 Switch off a FPGA block bug challenge specification change Simulate with a new model Macro3 disabled Macro3A Design finished! H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m

4. Semulator V2.4dsr4 of 16 Wave Window Development of complex FPGA and ASIC debugging Testbench HDL Simulator and Hpe Desk Hpe_midi H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m PCIeX4 over Cable debugging on hardware with trusted test bench

5. Semulator V2.4dsr5 of 16 Hardware in the Loop Hpe_midi Macro1 Macro n... Ext. Component e.g. CPU Hpe_child board Standard components can be implemented directly into simulation and emulation Testbench Files HDL Simulator and Hpe Desk Design File VHDL H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m Used for EmulationUsed for Simulation Controlled by a click in Hpe_desk

6. Semulator V2.4dsr6 of 16 Clock Acceleration* Testbench Files HDL Simulator and Hpe Desk Macro3Macro4 Hpe_midi Macro1Macro2 Controlled by user Clock Factory up to 100 MHz Simulator clock 20kHz – 200 kHz *International patent applied Individual clock for every macro Runs your Modelsim ® simulation in “real time” H D L S i m u l a t o r R a p i d P r o t o t y p i n g S y s t e m

7. Semulator V2.4dsr7 of 16 Faster Simulation The SEmulator can speed up your Modelsim simulation:

8. Semulator V2.4dsr8 of 16 Clock Factory You can program every clock source -> clock input by a click

9. Semulator V2.4dsr9 of 16 JTAG Debugger / Scanner You can read and write every pin of every component in the JTAG chain, customer specific chain in DUT is supported.

10. Semulator V2.4dsr10 of 16 What you need for SEmulation: A standard FPGA development system e.g. Hpe_midi A PCIe X4 over cable communication card e.g. Hpe_com1 Software package Hpe_desk includes SEmulator, Clock Factory Programmer, JTAG Scanner/Debugger, ALTERA Quartus And last but not least a PC and MENTOR Modelsim SE

11. Semulator V2.4dsr11 of 16 Advantages of SEmulation Early and continued testing of final hardware  Higher design quality / reliability Dramatically decrease RTL simulation time  Decrease development time Standard FPGA board for development, different boards available  No additional hardware cost Hardware in the Loop (Cosimulation)  Every external hardware can be implemented easily in the SEmulator ‘No’ limitation on pin and gate count  Broad family concept – Many extension boards

12. Semulator V2.4dsr12 of 16 Roadmap for 2008 Logic Analyzer Based on ALTERA’s Signal Tap we develop a Logic Analyzer for internal signals. The difference, we transfer the signals via our 10 Gbit PCI Express I/F to the PC. This allows higher number of signals for a longer time period. Fault Injector and Analyzer Together with the University of Vienna we develop a Hardware Fault Injector and the required analysis software. External SEmulator From Q2 2008 onwards we will deliver in addition an external SEmulator. A standard high speed connector on a board allow SEmulation, high speed Logic Analysis and Fault Injection on every FPGA. Or simple a high speed window into the FPGA for every kind of application.

13. Semulator V2.4dsr13 of 16 H u m a n I n t e r f a c e Internal and external LCD Connector Keyboard DIPLED FPGA Prototyping Area Clock Factory Reset Power Supply 3,3V 2,5V 12V Hpe_child Connector Hpe_child Connector Santa Cruz Connector USB2.0 FS-Host USB2.0 FS-Host USB2.0 FS-OTG Ethernet 10/100 RS232 LINCAN VGA 3 * 8bit PS2AC97 SD-Card FLASH 8M*32 SRAM 256k*32 EEPROM 2k bit 720 pin Hpe Module Connector 473 I/O plus Power Supply 6-12 bit D/A 6-12 bit A/D USB2.0 HS-Target Motherboard for FPGA development

14. Semulator V2.4dsr14 of 16 The Enclosure - Protect your hardware

15. Semulator V2.4dsr15 of 16 1 FPGA module for FPGA development with or without SEmulation 180.000 (340.000) Logic Elements = 1.8 (3,4) Mio ASIC gates *) Hardware in the Loop Every Child Board can be used for simulation and for emulation *) Figures in brackets are STRATIX3 values I/O manager can be added on request Clock Factory IP & SW Protection Controller Hpe_module1X Child Board High speed access L4 Hpe_module connector 473 I/O plus power supply Child Board EP2S180 DUT Common Config. Device ALTERA USB Blaster To PC Communication Controller PCIe X4 over cable Hpe_PCIe Child Board

16. Semulator V2.4dsr16 of 16 Child Board 2 FPGA module for FPGA development with or without SEmulation 360.000 (680.000) Logic Elements = 3.6 (6.8) Mio ASIC gates High speed access 2 * L4 Hpe_module connector 473 I/O plus power supply EP2S180 DUT Child Board EP2S180 DUT 512 single ended bus 128 LVDS pairs between every FPGA Common Config. Device ALTERA USB Blaster Clock Factory To PC IP & SW Protection Controller Hpe_module2X Communication Controller PCIe X4 over cable Hpe_PCIe Child Board