1. Data processor Status Giuseppe Osteria INFN Napoli Paris, March 2, 2012 Euso Balloon 4th progress meeting Giuseppe Osteria INFN Sezione di Napoli

2. Data processor: Subassembly items The DP functionality is obtained by connecting different specialized items, which form a complex system. The main subassembly items are:  Control Cluster Board (CCB)  Main processing unit (CPU)  Data Storage (DST)  Housekeeping system (HK)  Clock Board (CLKB)  GPS receiver (GPSR)  Data Processor Power Supply (DP-LVPS)

3. Data Processor: Block diagram DP LVPS DP LVPS 28V v SpaceWire 12V v RS232 v SATA Data Storage Visible cam (adv. opt.) Visible cam (adv. opt.) Space Wire to PCI v Gbit-Ether. or PCI GPS v HK system HK system v 5V 28V 5V CLKs,Sync, Trig RS232 PDM box PDM box v RS422 12V, 5V, 3.3V HL-CMD Analog (V, T) Fast parallel link SPI PWP V, T monitor 12V CCB CPU IR Camera (adv. opt.) IR Camera (adv. opt.) CLK board CLK board SIREN system v SpaceWire V, A Monitor

4. Data Processor: External interfaces  DP-Siren  CPU-Nosyca data telemetry interface  RS232?, RS422,? Ethernet? (undefined)  HK-Nosyca command interface  Telecommand, HL-CMD (undefined)  DP-TLS  HK-lenses/structure  Temperature sensors, heaters?, other? (undefined) A proposal for thermal sensors: 1-wire temperature sensors (Maxim DS18S20) Digital thermometer Oper. Temp. (°C) -55 to +125 Accuracy (± °C)0.5

5. Data Processor: External interfaces  DP- PDM  CCB-PDM-board data/command interface  Fast parallel link (40 MHz, 8 bit) for data PDM  CCB  SPI (2 MHz) for commands CCB  PDM  Clock/Control signals New broadcast signal proposed  HK-PDM-board  Analog lines (Volt.,Temp.), switch on/off (undefined)  HK-HV system  Analog, switch on/off, other?  DP- PWP  LVPS-PWP Meeting in Tuebingen on18 Feb. Details in Andrea’s talk

6. Data Processor: Internal interfaces  CPU- CCB  SpaceWire data/command interface  protocol level not yet defined  CLKboard-CCB  Clocks, trigger and broadcast signals (OK)  CPU-HK  RS422 data/command interface (TBC)  Temp. sensors (TBD)  HK- CLKboard, CCB, GPS Meeting in Tuebingen on20 Feb. Skype meeting on24 Feb. Details in Gustavo’s talk Meeting in Tuebingen on20 Feb.

7. Data processor subassembly – CPU - status: The CPU will be Commercially available Off-The-Shelf (COTS) component Two candidates have been selected: Arbor ITX-i2705 board based on Intel Atom Processor N270 (1.60 GHz) 2 SATA ports, RAID 0, 1 supported Power consumption 12 W Operating temperature -20° C to +70° C Eurotech Antares Core i7 EBX board. 5.25” Single board Computer based on Intel Core i7 620UE 1.06GHz processor 4 SATA ports, RAID 0, 1, 5 supported Power consumption 18-25 W Operating temperature -20° C to +60° C The two boards (already ordered) will be tested and their performance will be compared. After the comparison one system will be selected and will be considered the proto model of the EUSO-Balloon CPU. (end of May 2012) If the proto model of the EUSO-Balloon CPU would fulfill all the requirements then it will be considered the PFM of the CPU. The Arbor board The Antares board

8. Data processor subassembly – CPU - Arbor iTX-i2705 in our lab. Atom N270 (1.6 GHz, hypertrheading enabled) Intel 945Gse and ICH7M 1 GB ram (DDR2 533 MHz) SATA 1.5 controller with 2 ports NO fan (big heatsink) Mini-itx form factor

9. Data processor subassembly – CPU - Eurotech Antares in our lab. Core i7 u620 (1.06 GHz, dual core, hypertrheading enabled) Intel QM57M chipset 2 GB ram (DDR3 800 MHz) SATA 2 controller with 4 ports One little fan cpu (and two small heatsinks) 5.25 form factor

10. Data processor subassembly - DST- Description: (device ordered) 2 x 960 GB OCZ Colossus Plus SSD 960GB Max Performance Read: Up to 245 MB/s Write: Up to 250 MB/s Max 4k Write IOPS: 12,300

11. Data processor subassembly - DST- Description: (device delivered ) Interface: SATA 6Gbps / Backwards Compatible 3Gbps 512MB Onboard Cache Indilinx Infused™ TRIM Support Boot Time Reduction Optimization AES and Automatic Encryption SMART Support Proprietary Indilinx Ndurance™ Technology Low-Latency Seek Time: 0.06ms Read; 0.09ms Write Slim 2.5" Design 99.8 (L) x 69.63 (W) x 9.3 mm (H) Lightweight: 83g Operating Temp: 0°C ~ 70°C Ambient Temp: 0°C ~ 55°C Storage Temp: -45°C ~ +85°C Low Power Consumption: 1.98W active,1.15W standby Shock Resistant up to 1500G RAID Support MTBF: 1,250,000 hours Only 512 GB but: Less power required Less weight and volume (2,5 “) Faster The 1TB model will be available soon

12. Data processor subassembly – CPU - SSD in our lab. OCZ Octane 512 GB (MLC enterprise grade) Firmware E0688584 SATA 3 interface (compatible with 1.5 and 2) 400 MB/s seq. read – 250 MB/s seq. Write TRIM support 2 or 3 ssd in stand alone, raid1 or raid5 configuration

13. Data processor subassembly – CPU - Performance test: setup - Arbor Arbor board equipped with 2 SSD OS Scientific Linux 6.2 i386 Kernel 2.6.32-220 and ext4 filesystem Two ways to obtain data redundancy LVM mirror  “stable” from RHEL 6.1 onwards  Passtrough TRIM support MD device  STABLE software raid on linux  Does not support TRIM KERNEL PANIC UNDER LOAD! MD USED FOR RAID 1 and 5...

14. Data processor subassembly – CPU - SSD speed test – Arbor Single disk hdparm: 108 MB/s dd: 119 MB/s Raid1 device hdparm:101 MB/s dd:103 MB/s Ext4 on single disk dd114 MB/s Ext4 on raid1 device dd110 MB/s Sequential read (drop_cache on fs)

15. Data processor subassembly – CPU - SSD speed test – Arbor Ext4 on single disk 81 MB/s Low cpu load Ext4 on raid1 device 44 MB/s Cpu load 2 (!!!) Sequential write (dd bs=1M)

16. Data processor subassembly – CPU - SSD speed test – Arbor Iperf with a big server on the same switch 735 Mb/s as server, 600 Mb/s as client NFS 4 write on ext4 single disk 40 MB/s Raid1 device28 MB/s (and very high cpu load) Filesystem via nfs

17. Data processor subassembly – CPU - SSD speed test – Eurotech Single disk hdparm 185 MB/s dd 199 MB/s Raid1 device hdparm360 MB/s dd404 MB/s Raid5 device (3 ssd) hdparm400 MB/s dd422 MB/s Ext4 on single disk dd220 MB/s Ext4 on raid1 device dd420 MB/s Ext4 on raid5 device dd496 MB/s Sequential read (drop_cache on fs)

18. Data processor subassembly – CPU - SSD speed test – Eurotech Ext4 on single disk 205 MB/s Ext4 on raid1 device 201 MB/s Cpu load 0.4 Sequential write (dd bs=1M) Ext4 on raid5 device 203 MB/s Cpu load 0.65

19. Data processor subassembly – CPU - SSD speed test – Eurotech Iperf with a big server on the same switch 900 Mb/s as server, 900 Mb/s as client NFS 4 write on ext4 single disk 106 MB/s Raid5 device106 MB/s (and very low cpu load)  Gigabit port is the bottleneck in this test Filesystem via nfs

20. Data processor subassembly – CPU - Performance test summary  Write performance in RAID mode  Access via NFS simulates a process similar to the interface with SpaceWire (to be verified soon) DeviceArborEurotech Ext4 on raid144 MB/s201 MB/s Ext4 on raid5-203 MB/s NFS 4 on ext4 single40 MB/s106 MB/s NFS 4 on ext4 Raid128 MB/s106 MB/s NFS 4 on ext4 Raid5--106 MB/s 330 kB written in 12 ms at 28 MB/s 3 ms at 106 MB/s 8 ms at 40 MB/s

21. Data processor subassembly – CPU - Power measurement - Arbor Three voltages 12 V for CPU and SATA disks 5V and 3.3V for SATA Measured power12V5V Start up (CPU)14.4 W (peak)- Stand by (CPU)9.6 W- Start up (CPU +1 disk)14.4 W (peak)3.5 W Stand by (CPU +1 disk)9.6 W1 W Start up (CPU +2 disks)14.4 W (peak)7 W Stand by (CPU +2 disks)9.6 W2 W + Ethernet port10.3 W2 W + Installating O.S.13.2 W3W + Tets I/O on disks10 W5.5 W (peak) No current absorbed by SSD on the 3.3 V Infrared picture of Arbor board

22. Data processor subassembly – CPU - Power measurement - Eurotech Three voltages 12 V for CPU and SATA disks 5V and 3.3V for SATA Only 1 of the two CPU cores powered Measured power12V5V Start up (CPU)22 W (peak)- Stand by (CPU)8.4 W- Start up (CPU +2 disks)22 W (peak)7 W Stand by (CPU +2 disks)8.4 W2 W + Test I/O on disks10 W6.5 W (peak) + Stress test26 W6.5 W + Stress test (reducing power on core 50%) 20 W5.5 W

23. Data processor subassembly – CPU - Test in vacuum chamber- Arbor Arbor board equipped with 2 SSD disks Power supply currents monitored Ethernet connection (remote control) Mother board sensors monitored 2 external thermal sensors

24. Data processor subassembly – CPU - Test in vacuum chamber- Arbor 1 st test From 1020 mbar to 3 mbar in about 2.5 hours with CPU and disks just powered and monitored. Power supply currents stable Temperature max reached 56 °C Stress test on CPU started at 3 mbar and at 0,1 mbar. Temperature increase from 56 to 58 °C. CPU worked without problem 2 nd test Long run (18 hours) at 3 mbar stress test on CPU and disks running all time long Increasing of the temperature from 58 °C to 61 °C without any degradation of the performance Arbor CPU vacuum qualified

25. Data processor subassembly – CPU - Test in vacuum chamber- Eurotech Eurotech board equipped with 2 SSD disks Power supply currents monitored Ethernet connection (remote control) Mother board sensors monitored 2 external thermal sensors Impossible to work in vacuum heatsink not adequate for fanless operation. (80 °C at 1020 mbar without fan) Contact in progress with Eurotech To obtain a fanless version

26. Data processor subassembly – CPU - SpaceWire to PCI interface  SpaceWire PCI Mk2 manufactured by Star Dundee  Technical Specification:  Size Standard PCI board, 165 mm long (approx., excluding front panel)  Power +3.3V DC, supplied via PCI connector SpaceWire Ports Compliant to SpaceWire Standard (ECSS-E50-12A) and support RMAP (ECSS-E-ST-50-12C)  Number of SpaceWire Ports: 3  Maximum Speed: 200 Mbits/s  Data-Strobe skew tolerance: tested on all units to ±2 ns at data rate of 200 Mbits/s  Connectors: 9-pin micro-miniature D-type  LVDS signalling: Using Xilinx LVDS  PCI Interface 32-bit, 33 MHz EMC Now in our lab. (delivered yesterday) Test with Arbor CPU Will start next week

27. Data processor subassembly – CLKB - Description:  The clock signals are transmitted to the CCB by using differential LVDS point- to-point connections.  The FPGA will host the following interfaces to :  GPS receiver through a RS232 port (NMEA protocol).  1PPS pulse of the GPS receiver in order to synchronize, at level of 1 GTU, the apparatus with the UTC time.  CPU (Command and data interface via Space Wire)  HK (HK parameters: analog or via I 2 C or SPI serial protocol TBD)  Form factor: 3U Euro card (160 mm x100 mm x 25 mm )  An FPGA Xilinx Virtex5 XC5VLX50T (Industrial grade) will be used to implement all the required functionalities of the board.  Master clock:  40 MHz Temperature Compensated Crystal Oscillator  frequency stability of +/-1 ppm in the temperature range of -40°C to +85°C.

28. Data processor subassembly – CLKB - Design of the CLKB almost completed at INFN of Naples (review of mechanics and electrical interfaces still in progress)

29. Data processor subassembly – CLKB - Development plane  Design of the CLKB almost completed at INFN of Naples (review of mechanics and electrical interfaces still in progress)  PCB design will be completed by the end of March 2012  CLKB Proto Flight Model will be ready to be tested by the middle of October 2012  Development of the VHDL code will be done in parallel to the production (first validation of the code on the ml 505 evaluation board)  Integration and test of the interfaces with GPS system once it will be available)  Validation of the Space Wire interface with GRESB SpaceWire/Ethernet Bridge manufactured by Aeroflex Gaissler.  Testing shall be completed, under planned circumstances, by the end of December 2012.

30. Data processor subassembly – GPSR – Description:  A possible GPSR candidate is based on the SiRFstarIII™ 20-channel GPS SMD compact module/receiver  The ISM300F2-C5-V0004 module is programmed with HIGH ALTITUDE BUILD, and works at cold temperatures for ballon applications.  Maximum altitude of 42000 meters (137795 ft)  Avalaible interfaces:  SiRF Binary at 57600 baud on port A  NMEA at 4800 baud on port B  1 PPS output  ITAR-free component

31. Data processor subassembly – GPSR – status: The ISM300F2-C5-V0004 module, programmed with HIGH ALTITUDE BUILD, delivered by Inventek. Some modification needed in order to properly interface it to CLKB. A list of possible alternative models was discussed with Jean Evrard.

32. Data processor subassembly – GPSR – Development plane:  The GPS receiver will be ordered at mid of July  It will be delivered in one month to INFN-Na.  The interface between GPS receiver and CLK board will be tested as soon as the receiver will be delivered. The test will be performed by using the Virtex5 evaluation board ml505 and, once it will be available, the flight model of the CLK board.  Testing shall be completed by the end October 2012

33. Data Processor: Mechanics 6U Subrack with 3U Dividers. Sub assemblies hosted in Frame-type plug-in units 6U and 3U Frame-type plug-in units Micro D connectors (ITT or Glenair) Metallic guides and heat-spreader planes To be studied

34. Data Processor: Mechanics Thermal dissipation: for COTS components heat dissipation can be improved by using thermal GAP Pad between a PCB or substrate and a chassis, frame, or other heat spreader TYPICAL PROPERTIES OF GAP PAD 1500 PROPERTY IMPERIAL VALUE METRIC VALUE Density (g/cc) 2.1 2.1 Heat Capacity (J/g-K) 1.0 1.0 Continuous Use Temp (°F)/(°C) -76 to 392 -60 to 200 ELECTRICAL Dielectric Breakdown V (Vac) >6000 >6000 Dielectric Constant (1000 Hz) 5.5 5.5 Volume Resistivity (Ohm-meter) 10 11 10 11 THERMAL Thermal Conductivity (W/m-K) 1.5 1.5