1. M V Ganeswara Rao Associate Professor Dept. of ECE Shri Vishnu Engineering College for Women Bhimavaram Hardware Architecture of Low-Power ALU using Clock Gating 1

2. Contents  Problem identification  Introduction  Principal of Clock-Gating  Proposed Architecture  Result  Conclusions  References 2

3. Problem Identification With the scaling of technology, the need for high performance and more functionality is increases. Power dissipation becomes a major bottleneck for microprocessor systems design, because clock power can be significant in high performance systems. Present day General purpose microprocessor designs are faced with the daunting task reducing power dissipation. Since power dissipation is quickly becoming a bottleneck for future technologies. Lowering power consumption is important for not only lengthening battery life in portable systems. But also improving reliability and reducing heat removal cost in high performance systems 3

4. Clock power is a major component of microprocessor power, because the clock is fed to most of circuit blocks, including ALU. Total power dissipation of chip consists of two components. 1. Static power dissipation which is due to leakage current of transistor during steady state and it is very small so, it is neglected 2. Dynamic power dissipation which has two components a) Short circuit power dissipation which is a function of slew rate and by applying sharp clock edges, this power dissipation is very small and is neglected. b) Charge/ discharge power dissipation 4 Introduction

5. 5 Charge/ discharge power dissipation which is given by P = f.C L V dd V s Where f is the frequency of the clock, C L is the load capacitance, V dd is the supply voltage and V s­ is output swing. When output swing from 0 to V dd then P = f.C L V dd 2

6. Principle of Clock Gating 6

7. Proposed Architecture 7 OpcodeOperationActive functional block 0000Addition Arithmetic1 0001Subtraction 0010Increment 0011Decrement 0100Multiplication Arithmetic2 0101Add with carry 0110Clear Reg 0111Set Reg 1000NOT Logical1 1001AND 1010OR 1011EXOR 1100Shift left Logical2 1101Shift Right 1110Rotate left 1111Rotate right

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9. Result 9

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12. Conclusions 12 A Low Power ALU successfully captured using VHDL and implemented on Xilinx Sptran 3E FPGA. The proposed ALU can perform 16 functions, which include arithmetic, Logical and shift operations. The proposed ALU will dissipate 24mW of power at 15Mz of clock. The designed ALU core can be used in any high performance systems such as high speed processors. By employing Clock gating, we can design low power RISC processor which consumes less power at high execution speed.

13. References 13 1. T. Esther Rani, M. Asha Rani, Dr. Rameshwar rao, "Area optimized low power arithmetic and logic unit,"IEEE J Solid-State Circuits, pp.224-228. 2. T. Esther Rani, M. Asha Rani, Dr. Rameshwar rao, "Area optimized low power arithmetic and logic unit,"IEEE J.Solid-State Circuits, pp.224-228. 3. Chandrakasan, A., and Brodersen, Low Power Digital Design, Kluwer Academic Publishers, R., 1995. 4. B. Pandey and M. Pattanaik, "Clock Gating Aware Low Power ALU Design and Implementation on FPGA", 2nd International Conference on Network and Computer Science (ICNCS), Singapore, April 1-2, 2013 5. B. Pandey, J. Yadav, N. Rajoria, M. Pattanaik, "Clock Gating Based Energy Efficient ALU Design and Implementation on 90nm FPGA", International Conference on Energy Efficient Technologies for Sustainability-(ICEETs), Nagercoil, Tamilnadu, April 10-12, 2013 6. J. P. Oliver, J. Curto, D. Bouvier, M. Ramos, and E. Boemo, "Clock gating and clock enable for FPGA power reduction", 8th Southern Conference on Programmable Logic (SPL), pp. 1-5, 2012. 7. J. Shinde, and S. S. Salankar, "Clock gating - A power optimizing technique for VLSI circuits", Annual IEEE India Conference (INDICON), pp. 1-4, 2011. 8. J. Castro, P. Parra, and A. J. Acosta, "Optimization of clock-gating structures for low-leakage high- performance applications", Proceedings of IEEE International Symposium on Efficient Embedded Computing, pp. 3220-3223, 2010. 9. V. Khorasani, B. V. Vahdat, and M. Mortazavi, "Design and implementation of floating point ALU on a FPGA processor", IEEE International Conference on Computing, Electronics and Electrical Technologies (ICCEET), pp.772-776, 2012.

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