1. DBM DAQ Status Ales 20.12.2013

2. IBL DAQ Workshop Held previous week and first part of this week https://indico.cern.ch/conferenceDisplay.py?confId=287662 Most of IBL DAQ developers gathered at CERN Lot of progress has been made – Mostly on SW to support the calibration and tuning of FEI4 – DBM included in Calibration Console (both for running in pit and in SR1 test setup) – Still few steps missing to close the full data path and readout the IBL test staves and/or DBM test telescopes. Getting close… – BOC to ROS data path over SLINK has been established and tested – We installed additional ROSes and Fit Farm PCs in DAQ barrack next to SR1 DBM now has dedicated ROS, kindly provided by Markus Joos from TDAQ team Several additional BOC cards Rev D arrived at CERN – In coordination with IBL DAQ team, DBM is free to use the BOCs in VME crates – Also got 1 BOC card Rev B for table-top testing (currently seats in LJ office)

3. DBM Specifics I discussed at length possible DAQ scenarios in scope of ATLAS infrastructure with Paolo Morettini (Pixel/IBL DAQ expert) – We identified a couple of possible approaches I also had many discussions with IBL BOC Firmware designer (Marius Wensing, Wuppertal) – He raised a couple of concerns by integrating additional blocks into IBL BOC design – FPGA Timing closure problems already with pure IBL design – Possible solutions: Design additional DBM specific FPGA coprocessor board (FMC extension with Multi-Gigabit Links to main BOC FPGAs) Use professional FPGA compilers (Synopsys Synplify, available at CERN) – Xilinx-provided compiler not optimal

4. Reminder: DAQ HW Concept

5. Reminder: DAQ FPGA Block Diagram

6. IBL BOC Photo and FMC Ext. Connector FMC Extension Connector with MGT links, Not used for IBL

7. Extending IBL BOC capability by adding FMC co-processor modules (just an example card, not directly usable for us) Key Features 1.2GHz TMS320C6455 DSP 1.5V to 3.3V VADJ operation 16-pins debug/emulator header option Fully conduction cooled compliant GPIO header option (press-fit) HPC (High-Pin Count) 400-pin connector MIL-I-46058c compliant (optional) Onboard 512MB DDR2 memory VITA 57.1-2010 compliant Targeted Applications Co-processor applications Aerospace/Defense applications This particular module not directly applicable. It has High Pin Count (HPC ) connector. BOC has Low Pin Count (LPC) connector.