1. Programmable Logic Devices Tulika Mitra tulika@comp.nus.edu.sg Copyright © 2001 Tulika Mitra

2. 2 Embedded Systems Technology Programmable Processors Application Specific Processor (ASIP) Single purpose hardware

3. 3 Embedded System Technology Differ in their customization for the problem at hand total = 0 for i = 1 to N loop total += M[i] end loop General-purpose processor Single-purpose hardware Application-specific processor Desired functionality Vahid & Givargis

4. 4 General-purpose processors Programmable device used in a variety of applications  Also known as “microprocessor” Features  Program memory  General datapath with large register file and general ALU User benefits  Low time-to-market and NRE costs  High flexibility Example: Pentium, ARM, … IRPC Register file General ALU DatapathController Program memory Assembly code for: total = 0 for i =1 to … Control logic and State register Data memory Vahid & Givargis

5. 5 NRE and unit cost metrics Unit cost  the monetary cost of manufacturing each copy of the system, excluding NRE cost NRE cost (Non-Recurring Engineering cost)  The one-time monetary cost of designing the system total cost = NRE cost + unit cost * # of units per-product cost = total cost / # of units = (NRE cost / # of units) + unit cost Vahid & Givargis

6. 6 Application-specific processors Programmable processor optimized for a particular class of applications having common characteristics Features  Program memory  Optimized datapath  Special functional units Benefits  Some flexibility, good performance, size and power Example: DSP, Media Processor IRPC Registers Custom ALU DatapathController Program memory Assembly code for: total = 0 for i =1 to … Control logic and State register Data memory Vahid & Givargis

7. 7 Single-purpose hardware Digital circuit designed to execute exactly one program  coprocessor, accelerator Features  Contains components needed to execute a single program  No program memory Benefits  Fast  Low power  Small size Datapath Controller Control logic State register Data memory index total + Vahid & Givargis

8. 8 IC technology Three types of IC technologies  Full-custom/VLSI  Semi-custom ASIC (gate array and standard cell)  PLD (Programmable Logic Device) Vahid & Givargis

9. 9 Full-custom/VLSI All layers are optimized for an embedded system’s particular digital implementation  Placing transistors  Sizing transistors  Routing wires Benefits  Excellent performance, small size, low power Drawbacks  High NRE cost (e.g., $300k), long time-to-market Vahid & Givargis

10. 10 Semi-custom Lower layers are fully or partially built  Designers are left with routing of wires and maybe placing some blocks Benefits  Good performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k) Drawbacks  Still require weeks to months to develop Vahid & Givargis

11. 11 PLD (Programmable Logic Device) All layers already exist  Designers can purchase an IC  Connections on the IC are either created or destroyed to implement desired functionality  Field-Programmable Gate Array (FPGA) very popular Benefits  Low NRE costs, almost instant IC availability Drawbacks  Bigger, expensive (perhaps $30 per unit), power hungry, slower Vahid & Givargis

12. 12 Comparison TechnologyPerformance/ Cost Time until running Time to high performance Time to change code functionality ASICVery HighVery Long Impossible FPGAMedium LongMedium ASIP/ DSP HighLong GenericLow-MediumVery Short Not Attainable Very Short Speed Flexibility

13. 13 Roadmap PROM PLA PAL CPLD FPGA

14. 14 Reading Digital Logic Circuit Analysis and Design by Nelson, Nagle, Carrol, and Irwin : Chapter 5.3, 5.4, 5.5, 11.2 Architectures of FPGAs and CPLDs: A Tutorial by Stephen Brown and Jonathan Rose [ Available on the web: check out the link from lectures page]

15. 15 PLD Definition Programmable Logic Device (PLD):  An integrated circuit chip that can be configured by end use to implement different digital hardware  Also known as “Field Programmable Logic Device (FPLD) “

16. 16 PLD Advantages Short design time Less expensive at low volume Volume Cost Nonrecurring engineering cost PLD ASIC

17. 17 PLD Categorization PLD SPLD HCPLD FPGACPLD PLAPAL Simple PLD High Capacity PLD Programmable Logic Array Programmable Array Logic Complex PLD Field Programmable Gate Array

18. 18 Programmable ROM (PROM) 2 N x M ROM N inputM output Address: N bits; Output word: M bits ROM contains 2 N words of M bits each The input bits decide the particular word that becomes available on output lines

19. 19 Logic Diagram of 8x3 PROM Sum of minterms

20. 20 Combinational Circuit Implementation using PROM 000100 001010 010011 011100 100010 101001 110100 111010 I0 I1 I2 F0 F1 F2 F0 F1 F2

21. 21 PROM Types Programmable PROM  Break links through current pulses  Write once, Read multiple times Erasable PROM (EPROM)  Program with ultraviolet light  Write multiple times, Read multiple times Electrically Erasable PROM (EEPROM)/ Flash Memory  Program with electrical signal  Write multiple times, Read multiple times

22. 22 PROM: Advantages and Disadvantages Widely used to implement functions with large number of inputs and outputs Design of control units (Micro-programmed control units) For combinational circuits with lots of don’t care terms, PROM is a wastage of logic resources

23. 23 Programmable Logic Array k AND gates m OR gates k X m links m outputs n inputsn x k links n x k x m PLA has 2n x k + k x m links Sum of products Programmable AND array + programmable OR array

24. 24 PLA 4 X 6 X 2

25. 25 Logic Implementation with PLA Finite number of AND gates => simplify function to minimum number of product terms Number of literals in a product term is not important since we have all the input variables Sharing of product terms between outputs => multiple-output minimization

26. 26 Design with PLA

27. 27 Programmable Array Logic (PAL) Programmable AND array Fixed OR array  Each output line permanently connected to a specific set of product terms Number of switching functions that can be implemented with PAL are more limited than PROM and PLA

28. 28 PAL Logic Diagram

29. 29 PAL Implications Number of product terms per output > number of product terms in each sum-of- product expression No sharing of product terms between outputs

30. 30 Design with PAL

31. 31 CPLD Logic Block Logic Block Logic Block Logic Block I/O Programmable Interconnect

32. 32 CPLD Logic Block Simple PLD  Inputs  Product-term array  Product term allocation function  Macro-cells (registers) Logic blocks executes sum-of-product expressions and stores the results in micro-cell registers Programmable interconnects route signals to and from logic blocks

33. 33 Major CPLD Resources Number of macro-cells per logic block Number of inputs from programmable interconnect to logic block Number of product terms in logic block

34. 34 Structure of FPGA (Xilinx) Logic Block I/O Block Interconnect

35. 35 Configurable Logic Block CLB

36. 36 Logic Function Implemented as look-up table (LUT) K-input LUT corresponds to 2 K x 1 bit memory K-input LUT can implement any k-input 1- output logic function

37. 37 Configuring FPGA Configure CLB and IOB Configure interconnect Interconnect technology  SRAM  Anti-fuse (program once)  EPROM / EEPROM

38. 38 Programming Technology NameRe-programmableVolatile EPROMyes (out of circuit)no EEPROMyes (in circuit)no SRAMyes (in circuit)yes Antifuseno

39. 39 FPGA Applications Glue Logic (replace SSI and MSI parts) Rapid turnaround Prototype design Emulation Custom computing Dynamic reconfiguration

40. 40 PLD Logic Capacity SPLD: about 200 gates CPLD  Altera FLEX (250K logic gates)  Xilinx XC9500 FPGA  Xilinx Vertex-E ( 3 million logic gates)  Xilinx Spartan (10K logic gates)  Altera

41. 41 FPGA Design Flow Design Entry Design Implementation Design Verification FPGA Configuration

42. 42 Design Entry (DK1 in our case) SchematicHDL Compile Logic Equations Minimize Reduced Logic Equations (Netlist) Test vectors Simulation

43. 43 Design Implementation Input: Netlist Output: bitstream Map the design onto FPGA resources  Break up the circuit so that each block has maximum n inputs  NP-hard problem  However, optimal solution is not required

44. 44 Design Implementation (Cont.) Place: assigns logic blocks created during mapping process to specific location on FPGA  Goal: minimize length of wires  Again NP-hard Route: routes interconnect paths between logic blocks  NP-hard

45. 45 Design Implementation Techniques Simulated annealing Genetic algorithm Mincut method Heuristic method

46. 46 Design Verification & FPGA Configuration Functional Simulation Timing Simulation Download bitstream into FPGA