1. DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG

2. ANALOG TO DIGITAL CONVERTER USING VOLTAGE TO TIME CONVERSION

3. ECE-C STUDENTS (2011-2015 BATCH)

4. ANALOG TO DIGITAL CONVERTER An analog signal can be converted into digital signal by counting the pulses from a variable source whose frequency is dependent on analog input signal value. The counting is done for a fixed period of time

5. Alternatively, the pulses from a fixed frequency source can be counted for a variable period of time,and the time period is then dependent on the analog signal under conversion.

7. S/H CKRT G CL HIGH SPEED COUNTER ….. … bn b2 b1 integrator comparator Vc control voltage s. …..……………….….. …………………….. vi(t) vs vcl vg vi Digital outputs VR

8. S/H CKRT G CL HIGH SPEED COUNTER ….. … bn b2 b1 integrator comparator Vc control voltage s. …..……………….….. …………………….. vi(t) vs vcl vg vi Digital outputs VR

9. This circuit shows an A/D converter It employs an integrator,a sample and hold(S/H) circuit, a voltage comparator and a high speed counter. A negative reference voltage V R is applied to the integrator,which integrates the voltage V R and provides a positive polarity output. The analog signal input under conversion V I (t) is sampled at a rate fixed by the control voltage vc,and the sampled signal at any instant vi is applied as a input to the non- inverting terminal of comparator.

10. The integrator output vs is connected to the non inverting terminal of comparator. When the integrated voltage vs is less than the analog voltage sample vi,the comparator output is at positive saturation,or at logic 1. A fixed frequency clock vcl is applied to the high-speed counter through the AND gate G. The AND gate is enabled for the duration from t=0 when Vs=0 to the time t=T when vs=vi.

11. We know that Vs=Vrt/τ Where the time constant τ=RC for the integrator. Therefore,at time t=T when vs=vi, T=τV I /V R Assuming F C is the clock frequency,the count output N obtained during the time interval 0 to T is given by N=F C T=τF C V I /V R Hence, the count value N is proportional to V I.

13. 0 1 0 1 0 1 Vc Vg CL Vs Vi THTH TATA TATA

14. The operation of the circuit can be analyzed as follows. The sample-and –hold circuit samples the positive input voltage V i (t) for every T A. Then the sampled voltage V i (t) is held for a time duration indicated by T H.

15. 0 THTH TATA TATA

16. During the period TH, the switch S is held open,and the integrator operates with its output following a ramp voltage waveform Vs.

18. 0 1 Vc Vs Vi THTH TATA TATA

19. When Vs<Vi, the comparator output vg is at logic 1,and the gate G is at logic 1,and the gate G is enabled,with Vc in 0 state.this continues for a time interval T and during this time,the clock pulses are passed by the gate G to the high-speed counter. Thus the digital output of the counter is directly proportional to T. During the time interval T A, the gate is disabled,and the digital output is read from the counter. The switch S is closed during T A, and the capacitor discharges, resetting V S to 0 V thus starting a new conversion.

20. 0 1 0 1 0 1 Vc Vg CL Vs Vi THTH TATA TATA

21. Thank you