Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 Digital Logic Design (41-135) Chapter 6 Combinational Circuit Building Blocks Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2006.

Published byElfreda Andrews Modified over 8 years ago

Similar presentations

Presentation on theme: "1 Digital Logic Design (41-135) Chapter 6 Combinational Circuit Building Blocks Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2006."— Presentation transcript:

1 1 Digital Logic Design (41-135) Chapter 6 Combinational Circuit Building Blocks Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2006

2 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 2 Chapter Objectives Multiplexers Combinational subcircuits Encoding & decoding

3 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 3 2-to-1 Multiplexer f s w 0 w 1 (c) Sum-of-products circuit (b) Truth table 0 1 f s w 0 w 1 (d) Circuit with transmission gates w 0 w 1 f s (a) Graphical symbol f s w 0 w 1 0 1

4 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 4 4-to-1 Multiplexer (b) Truth table w 0 w 1 f s 1 w 0 w 1 00 01 s 0 w 2 w 3 10 11 0 0 1 1 1 0 1 fs 1 0 s 0 w 2 w 3 (c) Circuit (a) Graphic symbol f s 1 w 0 w 1 s 0 w 2 w 3

5 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 5 Larger Multiplexers 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f (a) 4-to-1 multiplexer(b) 16-to-1 multiplexer

6 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 6 Applications of Multiplexers: Crossbars x 1 0 1 x 2 0 1 s y 1 y 2 (a) 2x2 crossbar switch (b) Implementation using multiplexers x 1 x 2 y 1 y 2 s

7 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 7 Programmable Switch of FPGA (a) A FPGA cell (b) Implementation using pass transistors (c) Implementation using multiplexers Storage cell built by several TRs  Larger size

8 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 8 Synthesis of Logic Functions: XOR (a) Implementation using a 4-to-1 multiplexer f w 1 0 1 0 1 w 2 1 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 0 (b) Modification 0 1 0 0 1 1 1 0 1 fw 1 0 w 2 1 0 0 1 f w 1 w 2 w 2 f w 2 w 1

9 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 9 3-Input Majority Function (a) Modified truth table (b) Circuit w 3 w 3 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 f w 1 0 w 2 1 w 3 Output is true/false when a majority of inputs are true/false, respectively.

10 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 10 3-input XOR with 2-to-1 Multiplexers (a) Truth table 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 2 w 3  w 2 w 3  (b) Circuit f w 3 w 1 w 2

11 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 11 3-input XOR with 4-to-1 Multiplexers (a) Truth table (b) Circuit 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w f w 1 w 2 w 3 3

12 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 12 Shannon’s Expansion Theorem Any Boolean function can be written in the form Where cofactors are written by The complexity may vary depending on the choice of i

13 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 13 Multiplier Synthesis (b) Circuit 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 0 1 f w 1 w 2 w 3 w 2 w 3 + (a) Truth table f w 3 w 1 w 2

14 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 14 Examples 3-input majority function Example for

15 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 15 Expansion with Two Variables By using

16 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 16 Examples 6.6 (a) Using a 2-to-1 multiplexer (b) Using a 4-to-1 multiplexer

17 Digital Logic Design Ch.6 Combinational Circuit Building Blocks 17 Example 6.7 3-Input Majority Function w 2 0 w 3 1 f w 1

Download ppt "1 Digital Logic Design (41-135) Chapter 6 Combinational Circuit Building Blocks Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2006."

Similar presentations

Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.

Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.
ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.
EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 5 Programmable.

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 5 Programmable.
ECE 2373 Modern Digital System Design Exam 2. ECE 2372 Exam 2 Thursday March 5 You may use two 8 ½” x 11” pages of information, front and back, write.

ECE 2373 Modern Digital System Design Exam 2. ECE 2372 Exam 2 Thursday March 5 You may use two 8 ½” x 11” pages of information, front and back, write.
SYEN 3330 Digital SystemsJung H. Kim Chapter 2-1 1 SYEN 3330 Digital Systems Chapter 2 – Part 1.

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 1.
Multiplexers, Decoders, and Programmable Logic Devices

Multiplexers, Decoders, and Programmable Logic Devices
Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.

Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)

ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)
Any logic circuits can be transformed to an implementation where only NAND gates (and inverters) are used. The general approach to finding a NAND-gate.

Any logic circuits can be transformed to an implementation where only NAND gates (and inverters) are used. The general approach to finding a NAND-gate.
CS 105 Digital Logic Design

CS 105 Digital Logic Design
Shannon’s Expansion Muxes and Encoders. Tri-State Buffers  A tri-state buffer has one input x, one output f and one control line e Z means high impedance,

Shannon’s Expansion Muxes and Encoders. Tri-State Buffers  A tri-state buffer has one input x, one output f and one control line e Z means high impedance,
Instructor: Alexander Stoytchev CprE 281: Digital Logic.

Instructor: Alexander Stoytchev CprE 281: Digital Logic.
Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic.

Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic.
Figure 6.1. A 2-to-1 multiplexer.

Figure 6.1. A 2-to-1 multiplexer.
Transistors and Logic Circuits. Transistor control voltage in voltage out control high allows current to flow -- switch is closed (on) control low stops.

Transistors and Logic Circuits. Transistor control voltage in voltage out control high allows current to flow -- switch is closed (on) control low stops.
Logic Gates How Boolean logic is implemented. Transistors used as switches to implement Boolean logic: ANDOR Logic with Transistors.

Logic Gates How Boolean logic is implemented. Transistors used as switches to implement Boolean logic: ANDOR Logic with Transistors.
Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.

Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.
Apr. 3, 2000Systems Architecture I1 Systems Architecture I (CS 281-001) Lecture 3: Review of Digital Circuits and Logic Design Jeremy R. Johnson Mon. Apr.

Apr. 3, 2000Systems Architecture I1 Systems Architecture I (CS ) Lecture 3: Review of Digital Circuits and Logic Design Jeremy R. Johnson Mon. Apr.
Logic Gates Shashidhara H S Dept. of ISE MSRIT. Basic Logic Design and Boolean Algebra GATES = basic digital building blocks which correspond to and perform.

Logic Gates Shashidhara H S Dept. of ISE MSRIT. Basic Logic Design and Boolean Algebra GATES = basic digital building blocks which correspond to and perform.
EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 12: Multiplexers, Decoders, Encoders, Shift.

EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 12: Multiplexers, Decoders, Encoders, Shift.

Similar presentations

Ads by Google