TLK10002 Overview and Debug Procedure

TLK10002 Overview and Debug Procedure
Max Robertson September 2012

Agenda Device Overview Link Initialization Procedure
High Speed SerDes Architecture Clocking and Jitter Transfer Debug Procedure Design References

Section 1: Device Overview

TLK10002 Block Diagram (Channel A)

Transmit Data Path The Low Speed Side SERDES takes in 2 or 4 lanes of 8b/10b-encoded serial data, and outputs 2 or 4 10-bit-wide parallel lanes. These parallel lanes are byte aligned by the Channel Sync block and decoded back into 8-bit-wide data by the 8b/10b Decoder. The parallel lanes are aligned with one another by the Lane Align Slave (LAS) and are written to the TX FIFO in 32-bit (in 4:1 mode) or 16-bit (in 2:1 mode) chunks.

Transmit Data Path (cont’d)
The TX FIFO handles the transition from the Low Speed Side clock domain to the High Speed Side clock domain. Data exits the TX FIFO in 16-bit chunks, and is 8b/10b-encoded prior to reserialization. The High Speed Side SERDES takes the 20-bit wide parallel data and serializes it for transmission over physical media.

Receive Data Path The High Speed Side SERDES takes in a single lane of high-speed (up to 10 Gbps) serial 8b/10b-encoded data and deserializes it into a 20-bit wide parallel bus. The parallel data is byte aligned by the Channel Sync block and then decoded by an 8b/10b Decoded into a 16-bit wide bus. The 16-bit wide output from the decoder is written to a the RX FIFO.

Receive Data Path (cont’d)
The RX FIFO is read in 32-bit (in 4:1 mode) or 16-bit (in 2:1 mode) chunks by the Lane Align Master (LAM). The Lane Align Master splits the data bus into 2 or 4 8-bit wide parallel lanes, which are then 8b/10b encoded. The output of the 8b/10b Encoder is sent to the Low Speed Side SERDES, which serializes the parallel data into 2 or 4 low speed lanes.

1:1 Retime Mode In this mode, a data stream (up to 5 Gbps) is deserialized, passed through a FIFO (for retiming), and then reserialized. This mode contains no decoding or encoding, so it supports non-8b/10b encoded data.

Clocking Architecture
Each channel can operate with a separate reference clock. The Low Speed Side SERDES, core logic, and High Speed Side SERDES within a channel will all share a common reference clock. The High Speed Side SERDES provides two additional clock signals: HS_RXB_CLK_A/B: This is the byte clock that is recovered from the incoming serial data stream. Its frequency will equal the serial data rate divided by 20. VCO_CLOCK_A/B_DIV2: This is the VCO clock divided by 2. Its frequency will equal the reference clock multiplied by the PLL multiplier value. Any clock can be divided down and output through the differential CLKOUTA/BP/N pins.

Clocking Architecture Block Diagram

Loopback Modes Various loopback modes are available for system self-testing: Deep Remote Loopback Deep Local Loopback Shallow Remote Loopback Shallow Local Loopback

Pattern Generation and Verification
Pattern generation can be enabled on each transmitter (High Speed or Low Speed, Channel A or Channel B) Pattern verification can be enabled on each receiver (High Speed or Low Speed, Channel A or Channel B) The available patterns for the High Speed Side are: PRBS 27 – 1, 223 – 1, and 231 – 1 High Frequency (HF), Low Frequency (LF), and Mixed Frequency (MF) Continuous Random Test Pattern (CRPAT) long or short The available patterns for the Low Speed Side are: There is a built-in error counter that can be used for link BER testing. (This can be useful during Link Optimization.)

MDIO Operations The TLK10002 implements the MDIO interface defined by Clause 22 of the IEEE802.3 specification. Read operation: Write operation:

MDIO Operations (cont’d)
The PHY Addr field (PA[4:0]) is used to select which device should respond to the command. The PA[4:1] should match the PRTAD[4:1] pin settings PA[0] is used to select a channel (0 = Channel A, 1 = Channel B) The REG Addr field (RA[4:0]) corresponds to the register address to be read or written Write commands can be verified by read commands if desired, but this is not necessary for the write to take effect

Section 2: Link Initialization

Link Initialization The goals of link initialization are:
Determine the byte boundary of the data within each individual lane (channel synchronization) Determine how the bytes are aligned across multiple lanes (lane alignment) This is necessary for proper reconstruction of the higher data rate signal across multiple lower-speed lanes. How is the link initialized? A special proprietary data pattern is sent across the low speed lanes. This pattern is designed to facilitate easy byte delineation and lane alignment. This pattern is sent across all lanes simultaneously, so the initialization procedure is identical between 4:1 mode and 2:1 mode. Link initialization is complete when both sides of the low speed link assert a “Link Status OK” output.

When is Link Initialization Performed?
Device/System power up (after configuration/provisioning) Loss of Channel synchronization assertion on any enabled LS lane Loss of Signal assertion on any enabled LS lane SERDES PLL Lock Indication deassertion After device configuration change After software determined LS 8b/10b decoder error rate threshold exceeded After device reset is deasserted Anytime the LS receiver deasserts “Link Status OK”. Presence of re-ocurring higher level / protocol framing errors TI Information – Selective Disclosure TI Information – Selective Disclosure 18 18

Lane Alignment Block Diagram

4:1 Data Symbol Order (Ch A only)
20

2:1 Data Symbol Order (Ch A only)
21

Lane Alignment Components
Lane Alignment Master (LAM) Responsible for generating special lane alignment initialization pattern Resides in TLK10002 RX (one instance in CH A, one instance in CH B) Responsible for bringing up RX LS link between TLK10002 and FPGA Monitors RXA/B_LS_OK from Protocol FPGA LTS Resides in FPGA TX (one instance in CH A, one instance in CH B) Responsible for bringing up TX LS link between TLK10002 and FPGA Monitors TXA/B_LS_OK from TLK10002 LAS Lane Alignment Slave (LAS) Responsible for monitoring LAM lane alignment initialization pattern Performs channel synchronization per lane (1 CH < 4 Lanes) (Byte Rotation) Performs lane alignment (realignment of bytes across lanes) Resides in TLK10002 TX (one instance in CH A, one instance in CH B) Generates TXA/B_LS_OK for Protocol FPGA LTM Resides in FPGA RX (one instance in CH A, one instance in CH B) Generates RXA/B_LS_OK for TLK10002 LTM TI Information – Selective Disclosure TI Information – Selective Disclosure 22 22

Lane Alignment – Pattern
During Lane Alignment, the LS Transmitter (LAM) sends a repeating loop of the following 8b/10b encoded bytes simultaneously across all enabled LS lanes: /K28.5/ (CTL=1,Data=0xBC) Repeat Following Sequence of 12 Characters 4 times or more: /D30.5/ (CTL=0,Data=0xBE) /D23.6/ (CTL=0,Data=0xD7) /D3.1/ (CTL=0,Data=0x23) /D7.2/ (CTL=0,Data=0x47) /D11.3/ (CTL=0,Data=0x6B) /D15.4/ (CTL=0,Data=0x8F) /D19.5/ (CTL=0,Data=0xB3) /D20.0/ (CTL=0,Data=0x14) /D30.2/ (CTL=0,Data=0x5E) /D27.7/ (CTL=0,Data=0xFB) /D21.1/ (CTL=0,Data=0x35) /D25.2/ (CTL=0,Data=0x59) Return to beginning of link alignment pattern LAM continues until LS_OK asserted. Only /K28.5/ are matched, other /DXX.X/ are used as fillers and checked only for running disparity and invalid 8b/10b decodes (as in channel synchronization) Switch to real traffic is done right after /K28.5/’s upon alignment. TI Information – Selective Disclosure TI Information – Selective Disclosure 23 23

Channel Synchronization
The LAS (LS Receiver) performs synchronization per lane: Channel synchronization performed similar to IEEE Figure 36–9—Synchronization state diagram The goal of this step is to determine the byte boundary within each individual lane. The same procedure is used for channel synchronization on the low speed and high speed side. The state machine is shown on the following slide, and can also be found as Figure 10 on page 15 of the TLK10002 datasheet. TI Information – Selective Disclosure TI Information – Selective Disclosure 24 24

Channel Synchronization State Machine
TI Information – Selective Disclosure

Lane Alignment The LAS (LS Receiver) performs lane alignment across the lanes similar in fashion IEEE 802.3ae-2002 (XAUI) specification. XAUI only operates across 4 lanes, so modification is needed. State machine shown on following slide. Note: Comma (K28.5) is used for lane to lane alignment instead of XAUI /A/ character Lane alignment checking is not performed in LAS after lane alignment is achieved and LS_OK is asserted. Channel Synchronization is performed during link training and normal system operation. Only /K28.5/ are matched, other /DXX.X/ are used as distance fillers and checked only for running disparity and invalid 8b/10b decodes (as in channel synchronization) After LAM detects LS_OK asserted, normal system traffic is carried (instead of proprietary link training traffic). TI Information – Selective Disclosure TI Information – Selective Disclosure 26 26

Lane Alignment State Machine
TI Information – Selective Disclosure TI Information – Selective Disclosure 27 27

Lane Alignment FPGA Implementation
TI will deliver RTL modules to the customer: Lane Alignment Master (LAM) Lane Alignment Traffic Generator Mux 8b/10b encoder (FPGA Free IP, eg GTP wizard) Lane Alignment Slave (LAS) Lane Alignment (Skew buffer) Lane Alignment Monitor Channel Sync (FPGA Free IP, eg GTP wizard) 8b/10b decoder (FPGA Free IP, eg GTP wizard) TI Information – Selective Disclosure 28

Lane Alignment Master – I/O’s
Serial out data_lane_0_in [17:0] data_lane_0_out [19:0] 2:1 data_lane_1_in [17:0] data_lane_1_out [19:0] 4:1 data_lane_2_in [17:0] data_lane_2_out [19:0] data_lane_3_in [17:0] data_lane_3_out [19:0] LAM LS_OK_in FPGA Serial I/O in 20-bit mode four_lane_en_in LS_OK_in high = lane alignment achieved four_lane_en_in high = 4:1 selected, low = 2:1 selected data_lane_X_in [8:0] [8] = control, [7:0] = data data_lane_X_in [17:9] [17] = control, [16:9] = data TI Information – Selective Disclosure 29

Lane Alignment Master – Speed
4:1 mode: In 4:1 mode with 20-bit internal data path, a maximum bus speed of just 125Mhz is needed to achieve 10Gbps Equation to calculate bus speed will be: Bus Speed = (Serial Data Rate / 80) Mhz 2:1 mode: In 2:1 mode with 20-bit internal data path, a maximum bus speed of 250Mhz is needed to achieve 10Gbps Bus Speed = (Serial Data Rate / 40) Mhz 4:1 is recommended for higher data rates for ease of meeting timing in FPGA TI Information – Selective Disclosure 30

Lane Alignment Slave – I/O’s
Serial in data_lane_0_out [17:0] data_lane_0_in [19:0] 2:1 data_lane_1_out [17:0] data_lane_1_in [19:0] 4:1 data_lane_2_out [17:0] data_lane_2_in [19:0] data_lane_3_out [17:0] data_lane_3_in [19:0] LAS LS_OK_out four_lane_en_in FPGA Serial I/O in 20-bit mode LS_OK_out high = lane alignment achieved four_lane_en_in high = 4:1 selected, low = 2:1 selected data_lane_X_out [8:0] -- [8] = control, [7:0] = data data_lane_X_out [17:9] -- [17] = control, [16:9] = data TI Information – Selective Disclosure 31

Lane Alignment Slave – Speed
4:1 mode: In 4:1 mode with 20-bit data path, a maximum bus speed of just 125Mhz is needed to achieve 10Gbps Equation to calculate bus speed will be: Bus Speed = (Serial Data Rate / 80) Mhz 2:1 mode: In 2:1 mode with 20-bit data path, a maximum bus speed of 250Mhz is needed to achieve 10Gbps Bus Speed = (Serial Data Rate / 40) Mhz 4:1 is recommended for higher data rates for ease of meeting timing in FPGA TI Information – Selective Disclosure 32

Section 3: High Speed SerDes Architecture

TI Information – Selective Disclosure
SerDes Block Diagram TI Information – Selective Disclosure 34

Typical SerDes PLL Implementation
The PLL is used to take a reference clock signal and multiply it up to the serial bit rate – usually a 10x or 20x multiplier. This high-frequency clock is used by the transmitter to shift out the serial data. This clock is also input to the receiver’s CDR, which dynamically adjusts the clock’s phase so that it tracks timing variations in the incoming serial data. TI Information – Selective Disclosure 35

Jitter Transfer though PLL
There are two mechanisms for jitter to transfer through the PLL: Reference feed-through PLLs used in TI SerDes devices typically have a bandwidth of ~1-10 MHz. Phase noise that is within this bandwidth will transfer through the PLL and appear as jitter on the serial transmit output. Power supply ripple Noise on the power supply can also couple through to the PLL output. It is recommended to use low-noise supplies on the rails that are used to power the PLL, since it is one of the more sensitive analog components. TI Information – Selective Disclosure

Transmitter and Receiver
Typical serial interconnects (PCB traces, copper cabling, etc.) have increasing loss with increasing frequency. This uneven loss profile can distort the serial data and introduce jitter dB 5G 7.1G 3m -18.7 -24.8 4m -22.1 -28.6 5m -24.5 -31.1 6m -27.4 -35.1 7m -30.5 -38.4 TI Information – Selective Disclosure

Intersymbol Interference (ISI) in Time Domain
Tx pulse 100ps Rx Pulse 5m cable Rx Pulse 15m cable Amplitude drop and dispersion >500ps “tail” Pulse spreading causes Intersymbol Interference (ISI). Each transmitted pulse interferes with its neighbors The received signal is the convolution of the transmitted pattern and the symbol response. S(t): Transmit pattern, e.g. PRBS, SR(t): Channel symbol response TI Information – Selective Disclosure 38 38

Transmit Pre-Emphasis
TLK10002 uses a 4-tap FIR filter for waveform shaping (pre-emphasis): This effectively increases the high-frequency gain relative to the low- frequency gain, compensating for frequency-dependent loss in the transmission media (e.g., PCB traces or cables) TI Information – Selective Disclosure

Transmitter Output (4-inch FR-4 trace)
Total Jitter = .298 UI, PRBS 27-1, 4:1 Mode, RefClk=122.88MHz, Swing = 1260 mVpp, PRE = -5, POST1 = -10, POST2 = -7.5, AC-coupled TI Information – Selective Disclosure

Total Jitter = .339 UI, PRBS 27-1, 4:1 Mode, RefClk=122.88MHz, Swing = 1260 mVpp, PRE = -2.5, POST1 = -17.5, POST2 = 0, AC-coupled TI Information – Selective Disclosure

Total Jitter = .311 UI, PRBS 27-1, 4:1 Mode, RefClk=122.88MHz, Swing = 1430 mVpp, PRE = -5, POST1 = -15, POST2 = -2.5, AC-coupled TI Information – Selective Disclosure

RX Block Diagram Term FFE DFE T&H ADC Rx signal AGC control Data Slicer CDR Sampling phase TI Information – Selective Disclosure

Block Diagram Comments
The sampler interface (ADC) and all subsequent digital blocks (FFE and DFE) operate in the recovered clock domain. This is necessary to be able to track frequency offsets between the local (TX) rate and the received rate. The input Track and Hold stage (T&H) includes some analog equalization. The CDR updates the ADC sampling phase by adjusting the phase interpolator output. There are three control loops acting simultaneously: AGC: adjusts ADC gain so that the cursor amplitude is fixed at optimal level. Contains course amplitude adjustment via 6-dB attenuator. DFE: uses amplitudes of previously received bits to cancel out post-cursor ISI effects. CDR: adjusts sampling phase to find optimal sampling point. TI Information – Selective Disclosure

Automatic Gain Control
The automatic gain control (AGC) loop scales the input signal amplitude so that it is in the optimal range for the ADC input. This allows for the full-scale range of the ADC to be used. The AGC has both fine and course control: The fine control is done automatically by adjusting the ADC input stage bias point. The fine control will give an AGC value that is between 3 and Larger values are used for larger signal amplitudes and smaller values are used for smaller signal amplitudes. Once the AGC has settled to a value in this range, it will indicate that it is locked. The course control is done by enabling or disabling a 6-dB attenuator. The attenuator behavior is controlled by the HS_AGCCTRL parameter: 00 = after AGC first achieves lock, the attenuator state will not change 01 = the attenuator may toggle if the AGC loses lock (value changing rapidly or at limit of range) 10 = attenuator forced off regardless of feedback from AGC loop 11 = attenuator forced on regardless of feedback from AGC loop TI Information – Selective Disclosure

RX Equalization Feed-Forward Equalization (FFE) FFE is used to compensate for pre-cursor ISI effects. Since it cannot adapt based on data history, it is set manually by the user using the HS_EQPRE parameter: The setting 000 (1/9 cursor amplitude) corresponds to the greatest amount of equalization, and should be used for long (high-loss) channels. The setting 110 (13/9 cursor amplitude) corresponds to the least amount of equalization, and should be used for short (low-loss) channels. Decision Feedback Equalization (DFE) DFE is used to compensate for post-cursor ISI effects. The algorithm adapts the tap values of a 5-tap (equivalent) FIR filter based on the amplitudes of previously received bits. HS_EQLIM can be used to limit the amount of adaptation; HS_EQHLD can be used to “freeze” the DFE in its current state. (Most applications will not use these options.) TI Information – Selective Disclosure

Channel Symbol Response with and without FFE/DFE
Magnitude (mV) Time (UI) Pre-cursor amplitude influenced by FFE settings (controlled by HS_EQPRE) Cursor amplitude is regulated by AGC loop Post-cursor amplitudes are influenced by DFE settings (controlled by adaptive algorithm) TI Information – Selective Disclosure

Effect of HS_ENTRACK The HS_ENTRACK bit, when set, can improve the BER for short, low- loss links. It causes the Track and Hold stage to be fixed in “track mode,” which disables some of the built-in analog equalization in the device’s front end. This causes the amount of intersymbol interference (ISI) sampled by the ADC to be higher. The CDR algorithm uses ISI to determine if the sampling point is too early or too late, so this increased ISI can actually help the algorithm settle to an optimum sampling point for low-loss channels. TI Information – Selective Disclosure

CDR Operation: First Order Mode
The first-order mode is used by setting HS_CDRFMULT to 00. The CDR voting algorithm will take in 8-UI blocks of samples, then indicate whether the sampling clock phase needs to be advanced or delayed. The decision is based on how much of an influence is seen on the current bit from the two adjacent bits (“pre” and “post”). Each time the voting algorithm sends an instruction to advance or delay the phase, the instruction is stored in an accumulator. Once the number of instructions accumulated for a particular direction (advance or delay) matches the HS_CDRTHR value, the update will take effect. The magnitude of the update will be 1/48 UI. TI Information – Selective Disclosure

HS_CDRTHR: Possible Settings
00: Four Vote Threshold Four phase update commands must accumulate before they take effect. This gives the CDR its maximum first-order tracking ability. 01: Eight Vote Threshold Eight phase update commands must accumulate before they take effect. 10: Sixteen Vote Threshold Sixteen phase update commands must accumulate before they take effect. 11: Thirty-Two Vote Threshold Thirty-two phase update commands must accumulate before they take effect. This gives the CDR its minimum first-order tracking ability. TI Information – Selective Disclosure

CDR Operation: Second Order Mode
Second order tracking is enabled when HS_CDRFMULT is equal to 01 or 10. This mode is intended to be used in asynchronous applications where there may be a frequency offset between the local and remote reference clock sources. Second-Order Algorithm: Each time a phase adjustment is made by the first-order algorithm, it is accumulated as a signed value in a register. The second-order algorithm makes continuous phase adjustments at a rate proportional to the value stored in this register. When HS_CDRFMULT is 01, the maximum rate of updates is one per 32 UI. When HS_CDRFMULT is 10 (2x mode), this rate is doubled to one per 16 UI. Making more frequent updates means that the CDR tracking ability is increased. TI Information – Selective Disclosure

HS_H1CDRMODE The CDR determines the optimum sampling position for the serial data by either locking on to the point in the symbol response where the pre- cursor bit, h(-1), is 0 (HS_H1CDRMODE = 0) or to the point where the post-cursor bit, h(+1), is 0 (HS_H1CDRMODE = 1). HS_H1CDRMODE = 0 This setting is preferred for a majority of applications The CDR will adjust the sampling phase so that the sampled pulse response has zero pre-cursor amplitude This “zero” point (and therefore the CDR sampling position) will vary with different FFE (HS_EQPRE) settings, so it is important for these to be optimized for various links. TI Information – Selective Disclosure

HS_H1CDRMODE (cont’d) HS_H1CDRMODE = 1 This setting can give better performance for near-lossless links that do not have enough pre-cursor ISI for the CDR to detect The CDR will adjust the sampling phase so that the sampled pulse response has zero post-cursor amplitude So that DFE adaptation does not cause instability between the two loops, the DFE tap values are fixed in this mode (i.e., adaptation is disabled). Because of this, HS_H1CDRMODE = 1 should not be used for applications that benefit from post-cursor equalization. The right choice of HS_H1CDRMODE will depend on the shape of the channel’s pulse response. In a majority of applications, though, the setting HS_H1CDRMODE = 0 is more appropriate. TI Information – Selective Disclosure

Section 4: Clocking and Jitter Transfer

Recommended Clocking Architecture
Usable FIFO Depth is +/-10UI (Absolute 20UI) FPGA TLK10002 TLK10002 FPGA PLL CDR TX FIFO PLL CDR RX FIFO PLL CDR 200ppm CDR PLL RX FIFO CDR PLL TX FIFO CDR PLL CLKOUT REFCLK1 REFCLK0 BBU JC PLL REFCLK JC PLL RRU BBU REFERENCE CLOCK BBU CDR CLOCK TI Information – Selective Disclosure 55 55

Multi-Hop Topologies Chain Tree Ring Each RE will recover the clock that is embedded in the serial data link coming from up stream and use that clock to time its transmit links. Each link will contribute some jitter, and across several “hops” there is a risk of a large amount of jitter accumulating. Therefore, it is best to minimize the amount of jitter that is transferred from a receive link to a transmit link. TI Information – Selective Disclosure

TLK10002 + LMK04808 RRU Jitter Transfer
The following tests were intended to characterize how jitter is transferred through an RRU (RX to TX link) when using the TLK Gbps SerDes with the LMK04808 Jitter Cleaner. The TLK10002 CDR will track phase movements in the serial input data that are below a certain rate. This phase noise will transfer to the recovered clock output. Therefore, a jitter cleaner can be used to produce a clean clock that tracks the nominal rate corresponding to the incoming data but not any short-term phase variations. Since (lower-frequency) phase noise can couple through the TLK PLL, using a low-noise reference clock is the best way to reduce jitter on the transmitted output data. TI Information – Selective Disclosure

Test Set-up VXI Clock Generator The TLK10002 was configured in PRBS test mode at Gbps. The default TX settings were used. REFCLK0p/n JBERT TLK10002 Oscilloscope Gbps Gbps OUTP/N HSRXAp/n HSTXBp/n INP/N CLKOUTp/n REFCLK1p/n MHz MHz The J-BERT was configured to output a PRBS 27 – 1 data stream at Gbps with ~45 ps of broadband random jitter. This type of jitter is not easily eliminated by equalization. CLKINp/n CLKOUTp/n The LMK04808 EVM was used in its default configuration for MHz input and MHz LVPECL output LMK04808 TI Information – Selective Disclosure

Measurement 1: TLK10002 Serial Input
VXI Clock Generator REFCLK0p/n JBERT TLK10002 Oscilloscope OUTP/N HSRXAp/n HSTXBp/n INP/N CLKOUTp/n REFCLK1p/n The JBERT output was connected to an oscilloscope to measure the amount of jitter present on the incoming datastream CLKINp/n CLKOUTp/n LMK04808 TI Information – Selective Disclosure

Jittery Serial Input to TLK10002

Measurement 2: TLK10002 Recovered CLKOUT
VXI Clock Generator REFCLK0p/n JBERT TLK10002 Oscilloscope OUTP/N HSRXAp/n HSTXBp/n INP/N CLKOUTp/n REFCLK1p/n The TLK10002 recovered clock output was connected to a phase noise analyzer. CLKINp/n CLKOUTp/n LMK04808 TI Information – Selective Disclosure

Recovered Clock Output from TLK10002

Measurement 3: LMK04808 Clock Output
VXI Clock Generator REFCLK0p/n JBERT TLK10002 Oscilloscope OUTP/N HSRXAp/n HSTXBp/n INP/N CLKOUTp/n REFCLK1p/n CLKINp/n CLKOUTp/n The jitter-cleaned recovered clock from the LMK04808 was connected to a phase noise analyzer. LMK04808 TI Information – Selective Disclosure

Jitter-Cleaned Clock from LMK04808

Measurement 4: TLK10002 Serial Output
VXI Clock Generator REFCLK0p/n JBERT TLK10002 Oscilloscope OUTP/N HSRXAp/n HSTXBp/n INP/N CLKOUTp/n REFCLK1p/n CLKINp/n CLKOUTp/n The serial output from the TLK10002 was measured to see the amount of output jitter achievable with a very low-jitter reference clock LMK04808 TI Information – Selective Disclosure

Clean TX Output from TLK10002

Section 5: Debug Procedure

The Basics Make sure that the device is properly powered with 1.0 V (VDDD, VDDA_LS/HS, DVDD, VDDT_LS/HS, and VPP) and 1.5 V or 1.8 V (VDDRA_LS/HS, VDDRB_LS/HS, and VDDO[1:0]). These voltages should be measured as closely as possible to the device pins so that any voltage drop across the power distribution plane is accounted for. Make sure that a valid reference clock is applied: Must be compatible with the signaling levels and frequency range defined in the Electrical Characteristics table of the datasheet Should be low jitter (< 4 ps RMS from 12 kHz to 20 MHz) Should be continuous. Temporary stoppages in the clock signal could cause invalid data. It is good to issue a reset after any gaps in the clock. Make sure that the device responds to MDIO commands (issue a read command to any register and verify the proper value is returned). Make sure the provisioning sequences given in the datasheet (or by the GUI) are followed. TI Information – Selective Disclosure

Status Indicators The TLK10002 provides several status bits that can be used to diagnose errors in the system: F.0 HS_PLL_LOCK and F.1 LS_PLL_LOCK: These bits indicate whether or not the High Speed Side and Low Speed Side PLLs are locked. If these bits are low, check to make sure that the reference clock signal is valid. F.2 TX_LS_OK and F.3 RX_LS_OK: These bits indicate whether or not Lane Alignment has completed. If these bits are low, force a lane realignment. If the lanes cannot be aligned, check to make sure that the LAM/LAS implementation in the partner device is correct. F.4 RX_FIFO_OVERFLOW, F.5 RX_FIFO_UNDERFLOW, F.6 TX_FIFO_OVERFLOW, and F.7 TX_FIFO_UNDERFLOW: These indicate errors in the RX and TX FIFOs. Over/underflow conditions occur when there is a mismatch between the read and write clocks. If problems are found, check the reference clock signal. TI Information – Selective Disclosure

Status Indicators (cont’d)
F.8 HS_DECODE_INVALID: This bit indicates an error in the 8b/10b encoder. These errors may occur when a bit is improperly received. Bit errors can typically be eliminated by optimizing the transmit and receive settings. F.10 HS_CHANNEL_SYNC: Indicates that synchronization has been achieved by the High Speed Side receiver. If this bit remains low, check the reference clock signal and the incoming serial signal. The serial input must meet the amplitude and jitter requirements listed in the Electrical Characteristics of the datasheet, and must be 8b/10b-encoded with comma characters (e.g., K28.5) for alignment. F.13 HS_LOS: Indicates that the High Speed Side input signal is too low for the receiver to detect it. If this bit is low, make sure that the link (e.g., optical fiber, cable, or backplane) is properly connected and that the signal amplitude is within the datasheet spec. TI Information – Selective Disclosure

Link Optimization Link Optimization is the process of iterating through various transmit and receive settings to find which ones provide the best bit error rate. The TLK10002 EVM GUI automates this procedure, but it can be done manually through MDIO transactions if desired. This procedure is necessary to ensure a low-BER high speed link. Relevant high speed transmit settings are: HS_SWING: This is the transmitted signal amplitude. Typically lower swings (~470 mV) work well with short interconnects to optical modules and higher swings (~1000 mV) work well with lossier electrical interconnects. HS_TWPRE, HS_TWPOST1, and HS_TWPOST2: These parameters set the pre- and post-cursor tap weights for the TX waveform shaping. Typically only negative values of these parameters should be used. For short electrical connections, values close to 0 work best. More negative values can be used for longer electrical connections to correct for ISI. TI Information – Selective Disclosure

Link Optimization (cont’d)
Relevant high speed receive settings are: HS_EQPRE: This sets the amount of precursor equalization. Higher numeric values of EQPRE (such as 11/9 or 13/9) correspond to less equalization and should be used with low-loss interconnects. Lower numeric values should be used for high-loss interconnects. HS_ENTRACK: This bit forces the receiver ADC into track-and-hold mode, and can provide better performance when operating over low-loss interconnects. There are many other TX and RX settings that are defined in the Register Bit Definitions section of the datasheet. For each interconnect, there is a different set of values for these TX and RX settings that gives the best performance. These optimal values can be found by taking BER measurements while sweeping various settings. TI Information – Selective Disclosure

Section 6: Design References

Design References TLK10002 Board Design Guide This document provides recommendations on how to design PCBs for systems using the TLK It covers power supplies, high-speed interfaces, and the various control interfaces that are needed. TLK10002 EVM User’s Guide This document provides info on how to set-up the EVM for common laboratory tests. It also provides a full schematic and layout of the EVM board which can be used as a reference or starting point in developing PCBs. TLK10002 Datasheet The datasheet contains detailed descriptions of all the functional blocks of the device and provides the recommended conditions for operation. TI Information – Selective Disclosure

Thank you! TI Information – Selective Disclosure

TLK10002 Overview and Debug Procedure

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