1. Recovered-clock jitter analysis for Super B A. Aloisio, R. Giordano INFN and University of Naples ‘Federico II’ aloisio@na.infn.it rgiordano@na.infn.it

2. SuperB Workshop - Perugia, Jun.092 Overview Why studying the jitter ? Phase noise in frequency domain Most used coding schemes Effects of payloads and noise Comments & Conclusions After hours: ATCA setup @ Naples

3. SuperB Workshop - Perugia, Jun.093 Jitter in recovered clock Recovered-clock by the serial receivers may be distributed to HW clients. However: ADCs degradate SNR with sampling clock jitter TDCs lower their timing resolution PLL, DLL might not lock at all BER in serial transmission increases, SerDes eventually fails (see TTC experience at LHC) … and much more …

4. SuperB Workshop - Perugia, Jun.094 Phase noise in freq. domain

5. SuperB Workshop - Perugia, Jun.095 Rj from the phase spectral density S  (f-f c ) is the square of the average phase deviation per each 1Hz frequency window. Integrating it over a given bandwidth yields the contribution to the Rj RMS value of the frequency range Let f c be the carrier frequency. For negligibile amplitude noise and small phase noise, the single side band noise spectrum L(f-f c ) is proportional to phase noise spectrum S  (f-f c )

6. SuperB Workshop - Perugia, Jun.096 Source Analyzer block diagram Different from spectrum analyzers, specific for phase noise (timing jitter) analys up to 100 MHz bandwidth

7. SuperB Workshop - Perugia, Jun.097 Time vs. Frequency domain Minus:  Need a reference clock (non always available)  Need a model to separate Rj from Dj  Very high bandwith required, memory, specific SW tools  ps resolution, at best  Long acquisition times (hours) Plus:  Works on random signals (data streams)  Separates Dj sources Minus:  Only works on periodic signals (clocks)  Expensive …  No Dj separation (DCD, …) Plus:  fs resolution  Accurate signal integrity analysis  natural Rj from Dj separation  Very fast measurements  Also allows PLL, VCO, XTAL characterizations

8. SuperB Workshop - Perugia, Jun.098 Clock span Recovered-clock jitter depends upon frequency offset between Tx and RX 100 ppm offset (achievable with low cost XTAL) keeps the RMS jitter within 20ps larger offset doubles the jitter (up to 50ps)

9. SuperB Workshop - Perugia, Jun.099 Encoding schemes Patented by IBM, widely used in datacom links (i.e. Ethernet) specific codes for synch and controls Low-length runs, 25% overhead, symbol oriented, running disparity (RD) guaranteed 8b10b 64-bit scrambling CIMT BPM Adopted by the GBT project at CERN Randomized data traffic VERY LOW overhead, frame oriented with header, RD not guaranteed Patented by HP, used by Glink specific code for synch and controls 16-bit length runs, 25% overhead, symbol oriented, RD guaranteed Adopted by the TTC project at CERN NO specific code for synch and controls 50% overhead, symbol oriented, RD guaranteed

10. SuperB Workshop - Perugia, Jun.0910 Jitter vs. payload vs. noise Test have been made to measure recovered-clock jitter vs. payload and vs. noise on Rx Payloads: Binary counters (to emulate event ID distribution), pulse (to test trigger, enable, rst, …), Pseudo Random Word Sequence (PRWS, to test generic detector data traffic) Noise @ RX: I/O switching activity at 240 MHz, PRBS, counting sequences on FPGA pins close to the Serial I/O

11. SuperB Workshop - Perugia, Jun.0911 8b10b: payload dependency Deterministic jitter (Dj) sensitive to binary counter payload RMS Random jitter (Rj) nearly independent from payload: 21.0 ps Pulse transmission as good as PRWS Data scrambling suggested for best jitter performance counterPRWSpulse

12. SuperB Workshop - Perugia, Jun.0912 64-scrambling: payload counterPRWSpulse No jitter vs. payload effect due to data randomizing (scrambling) No Dj induced by data patterns RMS Random jitter (Rj) stable at 21.1 ps

13. SuperB Workshop - Perugia, Jun.0913 CIMT: payload counterPRWSpulse Very good pulse transmission (better than PRWS): Rj = 20.0 ps Deterministic jitter (Dj) lightly sensitive to binary counter payloads RMS Random jitter (Rj) quite sensitive to payloads

14. SuperB Workshop - Perugia, Jun.0914 BPM: payload counterPRWSpulse Deterministic jitter (Dj) lightly sensitive to binary counter payloads (yet better than G-Link) RMS Random jitter (Rj) nearly stable at 20.7 ps Best jitter performance at expenses of bandwidth

15. SuperB Workshop - Perugia, Jun.0915 Noise tests High-speed serial I/O is well shielded by power/ground pins 8-bit bus is used as aggressor, serial pins are victims Different patterns to emulate from random traffic to peak toggling activity Test immunity to internal logic activity, Simultaneous Switching Output (SSO) noise, xtalk on and off chip

16. SuperB Workshop - Perugia, Jun.0916 Jitter vs. Noise Worst case jitter is due to I/O pins toggling at line rate (240 MHz) 20% average jitter increase due to I/O activity at low frequency (<10KHz), quite hard to filter out For best performance, RX FPGA should be kept as quiet as possible 8b10b scrambling CIMTBPM I/O @ 240 MHz DC-DC Converters Rj RMS = 23.2 psRj RMS = 24.4 ps Rj RMS = 24.0 psRj RMS = 24.3 ps

17. SuperB Workshop - Perugia, Jun.0917 RMS jitter on recovered clock 8b10b is largely used in standard protocols: it would allow hybrid links Light dependency of phase noise from payload (scrambling is suggested for best performance) Good noise immunity Low overhead (25%) Controls and comma characters available Codec already developed. More sophisticated solutions available as IP Link lock policies tunable on different parameters: running disparity, commas, … Coding / patternsCounter (ps)PRWS (ps)Pulse (ps) 8b10b 21.0 20.9 CIMT 20.820.520.0 Scrambling 21.1 21.2 BPM 20.820.720.6 Coding vs.payload (no noise) Coding / patternsPRWS (ps)Toggle @ 240 MHz (ps) 8b10b 21.123.2 CIMT 20.924.0 Scrambling 21.524.0 BPM 21.124.3 Coding vs.RX noise (PRBS on TX)

18. SuperB Workshop - Perugia, Jun.0918 Conclusions FPGA high-speed serial links may provide the DAQ for a moderate jitter clock distribution network 8b10b is a viable coding scheme, which also opens the way to hybrid link (FPGA off-the-shelf SerDes) Frequency domain analysis is THE tool for clock jitter characterization Total Jitter is VERY DIFFERENT from RMS and it depends upon the requested BER level. Consider a factor 10 if a 10 -12 BER is required Jitter cleaners should be tested in order to filter the noise before distributing the clock to DAQ clients

19. SuperB Workshop - Perugia, Jun.0919 ATCA setup @ Naples (Antonio Ordine) ATCA setup: Dual-star ATCA backplane CPU running SLinux Switch Mezzanine Carrier board (not shown) Shelf manager On-going activity in view of the design of a nuclear physics experiment