1. Semiconductor Manufacturing Technology Silicon and Wafer Preparation

2. CZ Crystal Puller Crystal puller and rotation mechanism Crystal seed
Molten polysilicon
Heat shield
Water jacket
Single crystal silicon
Quartz crucible
Carbon heating element
Crystal puller and rotation mechanism
Figure 4.10

3. Photograph courtesy of Kayex Corp., 300 mm Si crystal puller
CZ Crystal Puller
Photograph courtesy of Kayex Corp., 300 mm Si crystal puller

4. Float Zone Crystal GrowthRF
Gas inlet (inert)
Molten zone
Traveling RF coil
Polycrystalline rod (silicon)
Seed crystal
Inert gas out
Chuck

5. Wafer Diameter Trends 300 mm 200 mm 150 mm 125 mm 100 mm 75 mm
3² ² ² ² ² ²

6. Wafer Dimensions & Attributes

7. Basic Process Steps for Wafer Preparation
Crystal Growth
Remove seed and
Other end of ingot
Wafer Slicing by diamond saw
Wafer Lapping and Edge Grind by Al2O3 and glycerine
Etching for removing surface damage
Polishing
Cleaning
Inspection
Packaging
Grinding to special diameter and ground some flat region

8. Ingot Diameter Grind Preparing crystal ingot for grinding
Flat grind
Diameter grind
Preparing crystal ingot for grinding

9. Wafer Identifying Flats

10. Wafer Notch and Laser Scribe
Notch
Scribed identification number
For crystals with diameters equal to or larger than 200mm no flats are ground. Instead, a small groove is ground along the length of the ingot

11. Polished Wafer Edge

12. Chemical Etch of Wafer Surface to Remove Damage

13. Double-Sided Wafer Polish
Upper polishing pad
Lower polishing pad
Wafer
Slurry

14. Quality Measures Physical dimensions Flatness Microroughness
Oxygen content
Crystal defects
Particles
Bulk resistivity

15. 2- Silicon Oxidation
Many different kinds of thin films are used to fabricate discrete device and integrated circuits.
The first important thin film in electronic device is oxide layer. This layer provides isolation from other device

16. 2- Silicon Oxidation
Using as a mask in film deposition (doping barrier)
Protection of wafer surface against wear and scratch (Surface passivation),
Isolation of devices from others (surface dielectric),
As a part in the MOSFET (Device dielectric).
Thermally grown oxides is also used as dielectric layer in capacitors between Si wafer and conduction layer.
Grow thin layer SiO2 in the gate region Si
Dopants
SiO2 layer as dopant barrier Si
SiO2 passivation layer

17. Wafer
Oxide layer
Metal layer
Dielectric use of SiO2 layer S D
Field oxide
MOS gate
source
Drain

18. Most applications of semiconductor are dependent on their oxide thicknesses
Silicon dioxide thickness, Å
Applications
60-100
Tunneling gates
Gates oxides, capacitor dielectrics
LOCOS pad oxide
Masking oxides, surface passivation
Field oxides

19. Types of oxidation Thermal oxidation High pressure oxidation
Anodic oxidation

20. 1- Thermal oxidation Chemical reaction of thermal oxide growth
Si (solid) + O2 (gas)  SiO2 (solid) (Dry oxidation)
Si (solid) + 2H2O(gas) → SiO2 (solid) + 2H2 (gas) (Wet oxidation)
Oxidation temperature C
Oxidation: Si wafer  placed in a heated chamber  exposed to oxygen gas

21. SiO2 growth stages Si wafer Initial
In a furnace with O2 gas environment
Oxygen atoms combine readily with Si atoms
Linear- oxide grows in equal amounts for each time
Around 500Å thick
Si wafer
Linear
Above 500Å, in order for oxide layer to keep growing, oxygen and Si atoms must be in contact
SiO2 layer separate the oxygen in the chamber from the wafer surface
Si must migrate through the grown oxide layer to the oxygen in the vapor
oxygen must migrate to the wafer surface
Si wafer
Parabolic

22. Parabolic relationship of SiO2 growth parameters
Linear oxidation
Parabolic oxidation of silicon
where X = oxide thickness, B = parabolic rate constant, B/A = linear rate constant, t = oxidation time
Parabolic relationship of SiO2 growth parameters
where B = SiO2 growth rate, X = oxide thickness, t = oxidation time
Thicker oxides need longer time to grow than thinner oxides
2000Å, 1200C in dry O2 = 6 minutes
4000Å, 1200C in dry O2 = 220 minutes (36 times longer)
Long oxidation time required:
Dry O2
Low temperature

23. Oxide thickness vs oxidation time for silicon oxidation in dry oxygen at various temperatures
Oxide thickness vs oxidation time for silicon oxidation in pyrogenic steam (~ 640 Torr) at various temperatures

24. Oxidation rate Controlled by: Wafer orientation Wafer dopant
Impurities
Oxidation of polysilicon layers
Large number of atoms allows faster oxide growth
<111> plane have more Si atoms than <100> plane
Faster oxide growth in <111> Si
More obvious in linear growth stage and at low temperature

25. Wafer dopant(s) distribution
Oxidized Si surface always has dopants; N-type or P-type
Dopant may also present on the Si surface from diffusion or ion implantation
Oxidation growth rate is influenced by dopant element used and their concentration e.g.
Phosphorus-doped oxide: less dense and etch faster
Higher doped region oxidize faster than lesser doped region e.g. high P doping can oxidize 2-5 times the undoped oxidation region
Doping induced oxidation effects are more obvious in the linear stage oxidation

26. High Pressure Oxidation
Problems in high temperature oxidation
Growth of dislocations in the bulk of the wafer  dislocations cause device performance problems
Growth of hydrogen-induced dislocations along the edge of opening  surface dislocations cause electrical leakage along the surface or the degradation of silicon layers grown on the wafer for bipolar circuits
Solve: low temperature oxidation BUT require a longer oxidation time

27. High pressure oxidation results in faster oxidation rate
High pressure system  similar to conventional horizontal tube furnace with several features:
Sealed tube
Oxidant is pumped into the tube at pressure atm
The use of a high pressure requires encasing the quartz tube in a stainless steel jacket to prevent it from cracking
High pressure oxidation results in faster oxidation rate
Rule of thumb: 1 atm causes temperature drop of 30C
In high pressure system, temperature drop of C
 This reduction is sufficient to minimise the growth of dislocations in and on the wafers

28. Advantage of high pressure oxidation
Drop the oxidation temperature
Reduce oxidation time
Thin oxide produced using high pressure oxidation  higher dielectric strength than oxides grown at atmospheric pressure
High pressure oxidation

29. 3- Photolithography
Photolithography is the process of transferring patterns of geometric shapes on a mask to a thin layer of photosensitive material (called photoresist) covering the surface of a semiconductor wafer.

30. Photolithography Process:
The first step in the photolithography process is to develop a mask, which will be typically be a chromium pattern on a glass plate.
Next, the wafer is then coated with a polymer which is sensitive to ultraviolet light called a photoresist.
Afterward, the photoresist is then developed which transfers the pattern on the mask to the photoresist layer.

31. Basic types of Photoresists.
1- Positive resists.
Positive resists decomposes ultraviolet light. The resist is exposed with UV light wherever the underlying material is to be removed. In these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer.
2- Negative resists
Exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. Therefore, the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions..

32. Basic types of Photoresists

33. Wafer Exposure Systems
Contact printing is capable of high resolution but has unacceptable defect densities. Inexpensive, diffraction effects are minimize.
• Proximity printing cannot easily print features below a few m (except for x-ray systems). Poor resolution due to diffraction effects, required 1 X mask.
• Projection printing provides high resolution and low defect densities and \ dominates today.

34. Wafer Exposure Systems
electronic
interface
computer
Stepper
E-Beam Lithography

35. Wafer Exposure Systems
Contact
Printer
Proximity
Projection

37. Photoresist Composition
The base resin is novolac (Phenol formaldehyde resin) a long chain polymer consisting of hydrocarbon rings with 2 methyl groups and 1 OH group attached.
The most commonly used positive resist consist of diazonaphtoquinone (DQ), which is the photoactive compound (PAC), and novolac (N), a matrix material called resin. Upon absorption of UV light, the PAC undergoes a structural transformation which is followed by reaction with water to form a base soluble carboxylic acid, which is readily soluble in basic developer (KOH, NAOH, TMAH etc.)

38. Off-axis Illumination technique
When the angle of illumination and the angle of diffraction are well matched, the amount of light diffracted can be enhanced and the contrast of the image improved.

39. Next Generation Lithography extreme ultraviolet : EUV
Uses very short 13.4 nm light
All reflective optics (at this wavelength all materials absorb!)
Uses reduction optics (4 X)
Step and scan printing
Optical tricks seen before all apply: off axis illumination (OAI), phase shift masks and OPC
Vacuum operation
Laser plasma source
Very expensive system

40. An extreme ultraviolet (EUV) lithography system.
Challenges:
EUV is strongly absorbed in all materials.
Lithography process must be performed in vacuum
Mask blank must also be multilayer coated to minimize its reflection.

41. Schematic representation of a proximity x-ray lithography system.
1nm
Advantages:
Low diffraction
Shorter exposure time
Scattering is minimum
X –rays pass through spots
Problems:
Masks are the most
Difficult and critical
Element of an XRL system
lacking of photoresist
1:1 printing
High energy x-ray destroy conventional optics

43. Although all non optical lithography techniques have 100 nm or better resolution , each process has its own limitations:
Proximity effect in electron beam lithography
Mask blank production difficulties in EUV lithography
Mask fabrication complexity in X-ray lithography
Random space charge effect in ion beam lithography

44. VLSI Silicon Devices resist silicon
O. Rohde, M. Reidiker, S. Schaffner, and J. Bateman, Solid State Technology vol. 29 no. 9 (Sept 1986)

45. 4- Etching
Etching is the process where unwanted areas of films are removed by either dissolving them in a wet chemical solution (Wet Etching) or by reacting them with gases in a plasma to form volatile products (Dry Etching).
Resist protects areas which are to remain. In some cases a hard mask, usually patterned layers of SiO2 or Si3N4, are used when the etch selectivity to photoresist is low or the etching environment causes resist to delaminate.
This is part of lithography - pattern transfer.

47. Pattern Transfer Method 1

50. Application of wet process
Silicon etching:
For semiconductor materials, wet chemical etching usually proceed by oxidation followed by the dissolution of the oxide by a chemical reaction.
For silicon, the most commonly used etchants are mixture of nitric acid (HNO3) and hydrofluoric acid (HF) in water or acetic acid (CH3COOH)
Si + 4HNO3 → SiO2 + 2H2O + 4NO2
Hydrofluoric acid is used to dissolve the SiO2 layer
SiO2 +6HF → H2SiF6 + 2H2O
Silicon dioxide etching
Dilute solution of HF with or without the addition of ammonium fluoride (NH4F) is used for wet etching.

51. Application of wet process
Silicon nitride and polysilicon etching
Silicon nitride films are etchable at room temperature in concentrated HF or buffered HF and in a boiling H3PO4 solution.
Selective etching of nitride to oxide is done with 85% H3PO4 at 180 oC because this solution attacks silicon dioxide very slowly. Silicon rate for silicon nitride is 10nm/min but less than 1nm/min for silicon dioxide
Gallium Arsenide Etching
The most commonly used etchants are the H2SO4-H2O2-H2O and H3PO4-H2O2-H2O.
For an etchant with an 8:1:1 volume ration of H2SO4:H2O2-H2O, the etch rate is 0.8 µm/min for <111> Ga face and 1.5 µm/min for all other faces.

53. Dry Etching ( Plasma assisted etching) Basic method of plasma etching

59. 5- Diffusion
Impurity doping is the introduction of controlled amount of impurity dopants into
Semiconductors.
The main goal of doping is changing the electrical properties of semiconductor.
Diffusion and ion implantation are the two key method of impurity doping a b
Comparison of (a) diffusion and (b) ion implantation techniques for the selective introduction of dopants into the semiconductor substrate.

60. Methods of planar process
Diffusion
A uniformly doped ingot is sliced into wafers.
An oxide film is then grown on the wafers.
The film is patterned and etched using photolithography exposing specific sections of the silicon.
The wafers are then spun with an opposite polarity doping source adhering only to the exposed areas.
The wafers are then heated in a furnace ( oC) to drive the doping atoms into the silicon.
Ion Implantation
A particle accelerator is used to accelerate a doping atom so that it can penetrate a silicon crystal to a depth of several microns
Lattice damage to the crystal is then repaired by heating the wafer at a moderate temperature for a few minutes. This process is called annealing.

61. Comparison of Diffusion and Ion Implantation
Diffusion is a cheaper and more simplistic method, but can only be performed from the surface of the wafers. Dopants also diffuse unevenly, and interact with each other altering the diffusion rate.
Ion implantation is more expensive and complex. It does not require high temperatures and also allows for greater control of dopant concentration and profile. It is an anisotropic process and therefore does not spread the dopant implant as much as diffusion. This aids in the manufacture of self-aligned structures which greatly improve the performance of MOS transistors.

62. An example of the chemical reaction for phosphorus diffusion using a liquid source is
4POCl3 + 3O2 → 2P2O5 + 6Cl2
The P2O5 forms a glass on silicon wafer and is then reduced to phosphorus by silicon:
2P2O5 + 5Si → 4P + 5SiO2
The phosphorus is released and diffuse in to the silicon, and Cl2 is vented.
Schematic diagram of a typical open tube diffusion system