1. FEC decoding algorithm overview VLSI 자동설계연구실 정재헌

2. Topics on Communication Modem Design VLSI Design Automation LAB2  Outline  Channel coding  Convolutional encoding  Trellis diagram  Viterbi algorithm  Methods of implementing VA  Trace-Back VA  Register-Exchange VA  Low-power, High-speed issues (TBVA vs REVA)  Project plan  Reference

3. Topics on Communication Modem Design VLSI Design Automation LAB3  Channel coding  Purpose  To find and correct errors from channel.  Basically, attach redundancy to original data.  Roughly, two kinds of codes. Block code & Trellis code.  Block code  Attach redundancy to data bits called block.  For more efficiency, extend redundancy.  Trellis code  Generally, use convolutional code.  Instead of using block, put data to shift register and get codeword from combinational logic.

4. Topics on Communication Modem Design VLSI Design Automation LAB4  Convolutional Encoding  Convolutional encoder example  K=3, rate=1/2, generating polynomial(7, 5)  Constraint length(K) means cardinality of register  State diagram + + SREG1SREG2 source bit codeword 00 01 10 11 0/11 1/11 1/00 0/10 0/01 1/01 1/11 0/00 input/codeword

5. Topics on Communication Modem Design VLSI Design Automation LAB5  Trellis diagram  Visualizing the transitions from state to state.  Finite-state diagram by a time-indexed.  Upper branch means input 0, lower branch means input 1.  Bits on branch means codeword. 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 … time 00 11 10 01 11 00 01 11

6. Topics on Communication Modem Design VLSI Design Automation LAB6  Viterbi algorithm  Maximum likelihood sequence estimation  Our objective is to estimate a 1 *, a 2 *,…, a X * signals of the sequence of transmitted symbols a 1, a 2,…, a X  We estimate the transmitted sequence to be the sequence that maximizes this likelihood.  Probability density function P[y(t), 0≤t≤τ | a 1 =a 1 *, a 2 =a 2 *,…, a X =a X * ]  MLSE and Trellis diagram  In trellis diagram, each state have N different probable path from another state.  Total N X path exist. (exponentially grow)

7. Topics on Communication Modem Design VLSI Design Automation LAB7  Viterbi algorithm(Cont'd)  Dynamic programming  Principle of optimality : Whatever the initial state is, remaining decisions must be optimal with regard the state following from the first decision. A B C E D F If ACEF is the shortest path, then ACE is the shortest path.

8. Topics on Communication Modem Design VLSI Design Automation LAB8  Viterbi algorithm(Cont'd)  VA is dynamic programming.  VA is maximum-likelihood algorithm.  Basic concept  Compare received signal with code for each path through the trellis.  Calculate Hamming distance or Euclidean distance.(choose by hard decision or soft decision)  Select path at minimum distance.  Performance issues  The number of comparisons.  Length on which decoding is performed.

9. Topics on Communication Modem Design VLSI Design Automation LAB9  Viterbi algorithm(Cont'd)  VA flow  Finding branch metric from received signal.  Compare summation of branch metric and path metric.  Select smaller distance path, called the ‘survivor’.  Update path metric and store survivor path.  Repeat indefinitely. 1. Branch metric calculation 002 011 101 110 00 01 00 1 5 3 11 1+2=3 5+0=5 3. Store survivor path : 00 And update path metric value. Incoming codeword 11 Incoming codeword 11 Hamming distances 2. Compare summation. 5>3

10. Topics on Communication Modem Design VLSI Design Automation LAB10  Viterbi algorithm(Cont'd)  Find maximum probability path from trellis diagram.  Total NX calculations required. 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 received codeword 1 0 5 1 2 2 0 1 0 2 2 2 1 1 2 2 10 1110 00 11 10 01 11 00 01 10 1 1 1 1 0 0 2 2 2 2 0 0 1 1 1 1 1 1 1 0 0 2 2 Branch metric Survivor path 1 Path metric ? ?

11. Topics on Communication Modem Design VLSI Design Automation LAB11  Methods of implementing VA  Trace-back VA  Write survivor path to memory. Use 4 banks.  Search start state to decode. Survivor path will be merged after training period.  Decode from searched state. Bank1Bank2Bank3Bank4 write1 search1write2 search2write3 decode1search3write4 write5decode2search4 search5write6decode3 search6write7decode4

12. Topics on Communication Modem Design VLSI Design Automation LAB12  Methods of implementing VA(Cont'd)  Register-exchange VA  A register is assigned to each state.  The register records the decoded output sequence along the path from the initial state to the final state.  At the last stage, the decoded output sequence is the one stored in the survivor path register that assigned to the state with the minimum path metric.

13. Topics on Communication Modem Design VLSI Design Automation LAB13  Low-power, High-speed issues  Power  TBVA uses 4*N*L bits memory. L means survivor path length and usually L=5K.  REVA uses N*L flip-flop and muxes. Each stage, flip-flop will be switched.  If L is large, REVA use more power because of switching.  Speed  TBVA needs trace back (search) operation.  Both needs training period L.  TBVA output first decoded bit after 3L clocks, but REVD output first decoded bit after L clocks.

14. Topics on Communication Modem Design VLSI Design Automation LAB14  Project plan weekplan 1Read papers. 2 3Make C simulator. 4 5Performance test of simulator. 6Fix parameters and final test of simulator. 7Implement to HDL, and compare with simulator. 8Make documents.

15. Topics on Communication Modem Design VLSI Design Automation LAB15  Reference  A.J.Viterbi, "Error bounds for convolutional codes and ssymptotically optimum decoding algorithm", IEEE Trans. Inform. Theory, vol It-13, pp.260-269, April 1967.  Ranjan Bose, "Information Theory, Coding and Cryptography", McGrawHill, 2003.  T.K.Truong, Ming-Tang Shih, Irving S.Reed, E.H. Satorius, "A VLSI Design for a Trace-Back Viterbi Decoder", IEEE Trans. Comm, vol 40, pp.616-624, March 1992.  Dalia A.El-Dib, Mohamed I.Elmasry, "Modified Register-Exchange Viterbi Decoder for Low-Power Wireless Communications", IEEE Trans. Circuits and Systems, vol 51, pp.371-378, February 2004.