1. Parallel compressing system for satellite on programmable chip Yifat Manzor Yifat Manzor & Reshef Dahan Supervisor: Eran Segev Part A

2. Satellite image Input Data rate from one sensor line   B/W Picture   Range – 2.5 km width   Velocity - 8 km/sec   4 Pixels per 1m ² Rate = 80 Mpix/sec Streaming Data 12-bit per pixel 5,000 pix 16,000 lines/sec 80 Mpixel image

3. System demands: » 80Mpix/sec input data rate. » Image width – 5000 pixel ADV202, compressing device in reversible mode, capabilities: » 27 Mpix/sec maximum input data rate » 25 MByte/sec maximum output rate » Maximum image width – 4096 pixel » Maximum image length – infinity

4. Solution MAIN IDEA To generate parallel processing by separating the picture to 3 compressors 1667pix 1666pix 3 16,000 lines/sec Tile

5. Memory ADV202 Rocket I\O System Description Xilinx ’ s development board – Virtex2Pro camera FPGA

6. FPGA block diagram Compressed data Rocket I/O DIVIDER Compression Unit MERGER

7. Implementation Modularity  Strip size and rate compatible with the compressor ’ s abilities.  Function block in design scalability  Merge and Divide protocol  Infrastructure for future systems requiring working in higher rates and/or handling larger image size.

8. Implementation Cont. Power saving in space  Compressing units – minimum as possible. possible.  Buffer in/out - minimum storing space.

9. Divider Separates the streamed data to 3 infinite, equal Separates the streamed data to 3 infinite, equal width strips. width strips. Separation technique - cyclic, streams 1/3 of Separation technique - cyclic, streams 1/3 of every line to a different compression unit. every line to a different compression unit. DIVIDER Compression Unit MERGER Compression Unit

10. Divider - Architecture compression unit 1 Divider_unit compression unit 2 compression unit 3 Rocket IO 80MHz

11. compression unit rate coordinator between the rate coordinator between the divider and the divider and the ADV202 input rate. ADV202 input rate. ADV202 model – imitates the ADV202 model – imitates the real ADV202 interface. real ADV202 interface. rate coordinator between the ADV202 output rate rate coordinator between the ADV202 output rate and the merger. and the merger. communicates with the merger for sending communicates with the merger for sending compressed data packages. compressed data packages. DIVIDER Compression Unit MERGER

12. 25MHz Compression unit - Architecture 27MHz funnel adv_202 model comp_data buff Interrupt_generator From divider 80MHz 8 bits12 bits To/from merger To merger 80MHz

13. merger Merges 3 streaming data Merges 3 streaming data channels to a single channels to a single streaming data. streaming data. Manages an interrupt queue. Manages an interrupt queue. Draws fixed size, compressed packages from the Draws fixed size, compressed packages from the compression units. compression units. Generates a header to every drawn package. Generates a header to every drawn package. DIVIDER Compression Unit MERGER compressed data package header Output Output :

14. Merger - Architecture header generator calculator 80MHz To/from unit 0 To/from unit 2 To/from unit 1 Compressed output 25MHz

15. Merger – Architecture cont. calculator Interrupt from unit 0 output generator queue generator queue To\from header generator Data to/from unit 0 Data to/from unit 1 Data to/from unit 2 80MHz Interrupt from unit 2 Interrupt from unit 1 25MHz Compressed output

16. Scalability aspect - 8 sensors lines ON BOARD POWER PC 1-2 /GLOBALMERGER DIVIDERMERGER Comp. Unit Comp. Unit Comp. Unit

17. Testing Environment DIVIDERMERGER Comp. Unit Comp. Unit Comp. Unit Virtex2Pro Generator Rocket I/O Check Results memory

18. Status Synthesis place & route Logic simulation (ModelSim) implementation Phasecomponent X√√Divider X√√ Compression unit X√√merger