1. Pierre PRAT Progress Meeting @APC the 12.10.2012 Michel DUPIEUX

2. Grounding Design is now stable after Johan Panh’s Remarks

3. Grounding principles In order to avoid ground loops: Use of galvanically isolated DC/DC converters Primary grounds (28V Battery) shall be connected on Mechanical ground of PWP Secondary grounds of DC/DC converters shall be connected on a single point on Mechanical ground of sub-equipments (DP, PDM) Mechanical grounds connected together Differential links (LVDS) between HK, CCB and PDM_Board, HVPS- 1

4. Harness shielding According to the recommendations of Johan Panh: Primary power supplies : twisted pairs, not shielded Secondary power supplies : LVPS-PDM PDM_Board : twisted pairs, shielded, with shielding connected to mechanical ground (360°) on each sides (HF immunity) HVPS-1 HVPS-2 : twisted pairs, shielded, with shielding connected to mechanical ground on HVPS-1 side and open on load (BF immunity) LVPS-HK, LVPS1-DP, LVPS2-DP HK, CCB, CLKB, GPSR, CPU, DST: twisted pairs, not shielded (TBC: internal connection of DP) Differential digital links: twisted pairs, shielded, with the shielding connected to mechanical ground (360°) on each side

5. 2222 2 2 2 2 2 2 HK 1 2 BAT_RET (P) 28V_BAT (P) GND_28V (S) GND_3.3V (S) 28V (S) 3.3V (S) GND_M HVPS-1 would have DC/DC converters to isolate the powers GND_M 0-2.44V STATUS ON/OFF 3 DAC 6 Differential signals (LVDS) ( x2 = 18 wires) between HK and HVPS-1 4 differential transmitters 2 differential receivers CS_DAC CS_IO HVPS-1 MISO MOSI SCK MOS I 6 bidirectional signals 6 status signals I/O expander s 4 differential receivers MISO Interrupt SCK Interrupt HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : 1 st flight version D-Sub 15 F D-Sub 15 M 6 C-W D-Sub 9 F D-Sub 9M BATTERY 3 C-W 6 x 14 HV lines 3 x 14 HV lines 9 9 3 3 STATUS 3 ON/OFF 3 0-2.44V GND_M HVPS-2 CS_DAC SCK MOS I CS_OUT 6 DAC 6 D-SUB 25 F D-SUB 25 M D-Sub 9 F D-Sub 9M 24 wires PDM_Board Micro-D 9 F Micro-D 9 M 4 differential receivers 4 differential transmitters 4 Differential signals (LVDS) ( x2 = 8 wires) between PDM_Board and HVPS-1 4 SWITCH COMMANDS 2 differential transmitters

6. HVPS Architecture and I/F are now stable: 2 HVPS boxes in PDM box: HVPS-1: 2 CV DC/DC (28V & 3.3V) for ground isolation SPI I/F with HK, LVDS I/F with PDM-Board (switch pulses), 3 DACs (HV tuning), 3 Cockcroft-Walton Converters. HVPS-2: 6 DACs (HV tuning), 6 Cockcroft-Walton Converters.

7. Electrical Interfaces are clearly defined (connectors, pinout Ok) Subd25 or 37? Subd25 or µSubd9?

9. Pinout and connectors need to be checked and update very soon CPUCCBCLKbGPSrHKLVPS1LVPS2LVPS3PDLVPSPDMPWPSIRENTLS CPU- MDM DB9 - DB9 + DB9 DB15-----RJ45- CCB MDM DB9 - MDM DB15 -DB15-DB9-- MDM DB51 --- CLKb MDM DB9 MDM DB15 - MDM DB9 DB15-DB9------ GPSr-- MDM DB9 -DB15-DB9------ HK DB9 + DB9 DB15 - MDM DB15 -DB9?3 x DB9 LVPS1DB15--- -----DB9-- LVPS2-DB9 DB15-----DB9-- LVPS3----DB15-------- PDLVPS----DB15---- PDM- MDM DB51 --DB15--- DEMM9S DB9+DB15 ---- PWP-----DB9 --?- SIRENRJ45---DB9------- TLS3 x DB9-

10. LVPS-PDM Pinout and connectors between PDM_Board and EC_Asic are checked GND_5V_EC (S) 5V_EC (S) EC-ASIC 3.3Vd_EC (S) 1.5V_EC (S) GND_1.5V_EC (S) GND_3.3Vd_EC (S) 3.3Va_EC (S) GND_3.3Va_EC (S) FPGA GND_M Connector PDM-LVPS GND_5V_PDMB (S) 5V_PDMB (S) PDM BOARD TES 1-0511V Regulator 1.5V GND_M 3.3V EC_ASIC 1 FPGA ground should be linked to the GND_M GND_1.5V_EC should be linked to the gnd of the FPGA 1V 1.8V Connector PDM_EC_ASIC

11. Kapton cable Fixation screw MAPMT ASIC BASIC FASIC D 68 pins68 pins ASIC A 68 pins68 pins ASIC C ASIC E 120 pins ABCDEF 68 pins68 pins 68 pins68 pins 68 pins68 pins 68 pins68 pins EC_HV Interfaces with:  CCB µSubd51  HVPS µSubd9  HK µSubd9? Subd25 on HK?  POWER Subd9

12. PWP2-Outside Power 22W?? Which dimensions PWP1-Inside Power 250 W ?? All connectors on a single side PWP-outside PWP-Inside 9 pins Sub-D connector To IR-CAM To LVPS-DP1 LVPS-DP2 LVPS-PDM LVPS-HK HVPS1 Plus two additional

13. Battery Cells, Connectors and Cables Cells Connectors Cables Option I: In case of 90W power consumption it will be necessary 20 cells of Saft G62/1.2 Option II: In case of 250W power consumption it will be necessary 50 Cells of Saft G62/1.2 The Connectors we are going to use are 9 pins D-Sub connectors for all interfaces and subsystems. The Cables we are going to use are THERMAX MIL-DTL-22759/91,92 for all interfaces and subsystems.

14. InterfacePower Consumption IR Camera22W High Voltage Power Supply2W LVPS DP17.2W LVPS DP27.2W Housekeeping6W LVPS-PDM2.4W CPU14.4W CCB5W Data Storage18W GPS1.2W CLK3.6W Additional Spare15W HeatersTBC Total: 111.2W+20% of security Margin = 133.4W Additional Heaters and backup = 70W (150+60)+20% of security Margin = 243.6W This version should be discussed 250W Interface Power Consumption IR Camera22W High Voltage Power Supply + Switches 2W Housekeeping6W CCB5W LVPS DP17.2W LVPS DP27.2W LVPS-PDM2.4W Additional Spare15W Total Power Budget: 74W+20% of Security Margin = 90W 90W - Which congiuration for Baseline? - Which power for Pack2 for IR Camera?

15. Short circuit risk? - Femeale connector on power side - PinOut of External Power - Common Ground or Ground Switching ? - Pinout Compatibility with LVPSs and HVPS1 ? - IR Camera the same way with separate Battery? - Who Provides Material and cables? Femeale connector?

16. Secondary subassembly Main Component Secondary subassembly Battery Pack Assembly Tests Battery Pack Packing CABLING FUSES Riken Institute Battery Pack +Fuse, switch and cabling integration SWITCHE S INTEGRATION WITH MECHANICS Post-integration tests Battery Pack Riken Institute Battery Pack assembly sequence

17. Electrical Interfaces are clearly defined (connectors, pinout Ok) HK DP 232/422

18. Who provide cables between:  HK and SIREN ?  HK and DP ?  PDM and DP ?  DP and SIREN ?  PWP_1 and LVPS (4)?  PWP_1 and HVPS_1?  LVPS_PDM and PDM?  HK et HVPS_1?  PDM_and HVPS_1?  CCB and PDM_board?  HK et PDM Board?  IR Camera ?

19.  Which Power budget PWP_1 ?  Clarify Power Pack interfaces.  Who provides Batteries (PowerPack 1 and Power Pack 2 ?  Clarify internal and external interfaces for DP (update Synoptic).  Define cables, providers ?  Use in general Femeale connector on Fixed on boxes exept for power side to avoid short circuit risk!!!  Documentation