1. AT91 Hardware and Power considerations

2. Power Supply considerations

3. 3 Double Power Line (except for the AT91x40 family) : –I/O lines VDDIO –Chip core VDDCORE Dedicated Power Lines : –Oscillator and PLL cells VDDPLL –Analog peripherals ADC and DAC VDDA –RTC, the 32768 Hz oscillator and the Shut-down Logic of the APMC VDDBU Powering the AT91 (1/3)

4. 4 Constraints –VDDIO  VDDCORE –VDDPLL  VDDCORE –VDDA  VDDCORE VDDIO and VDDCORE are separated to permit the I/O Lines to be powered with 5V, thus resulting in full TTL compliance. Powering the AT91 (2/3)

5. 5 Powering the AT91 (3/3) Example : AT91M55800A AT91M55800A Memories DC/DC Converter 3.3V VDDIO VDDCORE Triple Supply with Shut Down Control VDDBU SHDNSHDWAKEUP Any kind of wake-up signal 2.7V Level Shut Down Control Signal Battery 32KHz Crystal 16MHz Crystal

6. Reset considerations

7. 7 Two external reset inputs: –NRST microcontroller reset pin –NTRST JTAG/ICE reset pin (not available on the AT91x40 family) Internal reset can also be generated by the watchdog and by software (EBI remap function allows dynamic reset vector) Reset sources: Resetting the AT91

8. 8 NRST is an active low-level input. It is asserted asynchronously but exit from reset is synchronized internally to the MCK. MCK must be active for a minimum of 10 clock cycles up to the rising edge of NRST External (NRST) or Internal (Watchdog) Reset Request –Test the Reset Status Register in the Special Function Module –If reads 0x6C : Cause of Reset is External NRST Pin assertion –If reads 0x53 : Cause of Reset is Internal Reset from Watchdog Reset detection

9. 9 Tri-state mode –To enter tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST –For normal operation, the pin NTRI must be held during reset by a resistor of up to 400KOhm Boot Mode Select –The input level on BMS pin during the last 10 clock cycles before the rising edge of NRST selects the boot memory Constraints on Reset and related signals (1/2)

10. 10 JTAG/ICE Debug mode –JTAGSEL pin is sampled at Power-Up: The JTAG/ICE debug mode is enabled when JTAGSEL is low JTAG Boundary-scan is enabled when JTAGSEL is high Constraints on Reset and related signals (2/2)

11. Clock considerations

12. 12 The AT91x40 Family, the AT91M63200 and the AT91M43300 have a MCKI input pin on which a crystal oscillator has to be connected. The AT91M42800A has 1 embedded oscillators: –The Slow Clock Oscillator It has been designed for use with a 32.768 kHz fundamental crystal, The oscillator integrates an equivalent load capacitance equal to 10 pF. Clock Connections (1/3)

13. 13 The AT91M55800A has 2 embedded oscillators: –The RTC Oscillator powered by the backup battery voltage supplied on the VDDBU pins. The XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal, The oscillator has been especially designed to connect to a 6 pF typical load capacitance crystal and does not require any external capacitor, as it integrates the XIN32 and XOUT32 capacitors to ground For a higher typical load capacitance, two external capacitances must be wired. Clock Connections (2/3)

14. 14 –The Main Oscillator, which provides a clock that depends on the frequency of the crystal connected to the XIN and XOUT pins The Main Oscillator is designed for a 3 to 20 MHz fundamental crystal, The oscillator contains 25 pF capacitances on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a crystal with a load capacitance of 12.5 pF is used. Clock Connections (3/3)

15. Oscillator considerations

16. 16  The crystal manufacturer specifies the typical load capacitor,  [internal load capacitor] + [external load capacitor] + [stray capacitor] must be equal to the specified load capacitor for the crystal. Pierce oscillator C 1in t C 2in t C 1ext C 2ext Crystal Bias resistor X IN X OUT

17. 17 Slow Clock Oscillator –Frequency running : 32.768 kHz typical –Maxi. current dissipation: 9 µA –Internal capacitance between [Xin]-[GND] or [Xout]-[GND]: 20 pF (per pin) or a Internal Equivalent Load Capacitance of 10 pF –Start-up time: 1.5 s (depends on the crystal quality) –On-chip bias resistor AT91M42800A Oscillator

18. 18 RTC Oscillator –Frequency running : 32.768 kHz typical –Very Low Power Design: less than 1 µA –Internal capacitance between [Xin]-[GND] or [Xout]-[GND]: 12 pF (per pin) or a Internal Equivalent Load Capacitance of 6 pF –Start-up time: 700 ms (depends on the crystal quality) –On-chip bias resistor –The AT91M55800A starts from the slow clock source, this oscillator must always be implemented => V DDBU must always be powered. AT91M55800A Oscillators (1/3)

19. 19 Main Oscillator –Frequency running with large bandwidth: 3 to 20 MHz –Low Power Design –Internal capacitance between [Xin]-[GND] or [Xout]-[GND]: 25 pF (per pin) or a Internal Equivalent Load Capacitance of 12.5 pF –Shutdown mode capability –Bypass mode capability. In this state, the external clock must be fitted on Xin input. The input bandwidth is: some kHz to 33 MHz. –On-chip bias resistor AT91M55800A Oscillators (2/3)

20. 20 –Startup Time : –Dedicated counter OSCOUNT in the Advanced Power Management Controller which indicates when the startup is finished. AT91M55800A Oscillators (3/3) (in MHz) (in ms)

21. PLL considerations

22. 22 One oscillator (Low Frequency) Two PLLs –PLL A, which provides a low-to-middle frequency clock range –PLL B, which provides a middle-to-high frequency range AT91M42800A PLLs (1/2)

23. 23 Two PLLs are integrated in the AT91M42800A in order to cover a larger frequency range. Both PLLs have a dedicated pin (PLLRCA or PLLRCB) which must be connected with an appropriate second order filter made up of one resistor and two capacitors. Dedicated counter PLLCOUNT in the Power Management Controller which indicates when the transient state is finished (settling time). AT91M42800A PLLs (2/2)

24. 24 Two oscillators –Slow Clock Oscillator –Main Oscillator One PLL to reach the maximum clock frequency AT91M55800A PLL (1/2)

25. 25 Multiply the Main Oscillator frequency by a number up to 64 to reach the maximum frequency. Dedicated PLLRC pin which must be connected with an appropriate second order filter made up of one resistor and two capacitors. Dedicated counter PLLCOUNT in the Advanced Power Management Controller which indicates when the transient state is finished (settling time). AT91M55800A PLL (2/2)

26. 26 Necessary time to reach stable state (overshooting frequency < 10% of the target frequency) PLL Settling time (in ms) (in MHz) R1 Value (in ohms) C1 Value (in nF) C2 Value (in nF) 59 1800 180 294 33 330 590 15 150 953 10 100 681 15 150 845 12 120 1130 33 330

27. 27 Automatic calculation Tools