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Published byTodd Boyd Modified over 8 years ago
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May 2006Andreas Steininger1 D istributed A lgorithms for R obust T ick S ynchronization
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May 2006Andreas Steininger2 Motivation chips (SoCs) are becoming distributed systems modular structure non-negligible inter-module communication delays increasing need for fault tolerance smaller critical charges shrinking timing margins lower voltage swing higher complexity
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May 2006Andreas Steininger3 The synchronous paradigm concept: precise global notion of time for entire chip method: discrete evenly spaced time slices single crystal oscillator global, “phase accurate” clock tree costs: - cumbersome clock tree design (physical limits!) - considerable waste of power - single point of failure
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May 2006Andreas Steininger4 Our alternative: DARTS concept: set of synchronized distributed time bases method: distributed agreement algorithm implemented in HW (asynchronous) generates local clocks in synchrony result: - reasonable synchrony - clock net becomes uncritical - no single point of failure
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May 2006Andreas Steininger5 Tick synchronisation 1 s is excellent precision for distributed clock at 1GHz this means 360.000° phase shift phase synchronisation tick synchronisation clock synchronisation keep same frequency for all modules, AND deterministically accommodate significant skew
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May 2006Andreas Steininger6 DARTS architecture FU 1 FU 2 FU 3 data bus Clock tree TG algs TG network Distributed clock modules FU i augmented with simple local clock unit (TG alg) TG algs communicate over dedicated bus (TG network) to generate local clocks need 3f+1 modules to tolerate f arbitrary faults Synchronous solution
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May 2006Andreas Steininger7 Conceptual Advantages (1/2) best possible synchrony locally: still (phase)synchronous remain with traditional synchronous paradigm globally: frequency synchronous global precision is known and bounded: delay max / delay min (relative!) completely avoid metastability issues
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May 2006Andreas Steininger8 Conceptual Advantages (2/2) clock generation with scalable fault tolerance fault tolerant clocking even with large skew weaker timing assumptions uncritical TG-net instead of clostly global clock tree closed-loop timing => frequency adapts to variation of operating conditions type variations from fab
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May 2006Andreas Steininger9 DARTS: Project Aims algorithm redesign appropriate HW design ASIC implementation demo application experim. evaluation
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May 2006Andreas Steininger10 DARTS: Project Aims algorithm redesign appropriate HW design ASIC implementation demo application experim. evaluation for „zero-bit“ messages formally proved
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May 2006Andreas Steininger11 DARTS: Project Aims algorithm redesign appropriate HW design ASIC implementation demo application experim. evaluation transition signaling logic
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May 2006Andreas Steininger12 DARTS: Project Aims algorithm redesign appropriate HW design ASIC implementation demonstrator design experim. evaluation FPGA prototype running
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May 2006Andreas Steininger13 DARTS: Project Aims algorithm redesign appropriate HW design ASIC implementation demonstrator design experim. evaluation time frame: 10/2005 – 10/2008
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