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Full Adders Vector Notation Multiplexers and Decoders Ellen Spertus MCS 111 September 6, 2001.

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Presentation on theme: "Full Adders Vector Notation Multiplexers and Decoders Ellen Spertus MCS 111 September 6, 2001."— Presentation transcript:

1 Full Adders Vector Notation Multiplexers and Decoders Ellen Spertus MCS 111 September 6, 2001

2 2 Full-adder Takes 3 inputs (a, b, carry-in) Produces 2 outputs (sum, carry-out)

3 3 Truth table for full-adder

4 4 Four cascaded full-adders

5 5 Vector notation A 0 is the least significant (rightmost) bit The leftmost bits are the most significant A 7 :A 0 indicates one byte (8 bits) Example: 10011100 BBB uses the notation a[7]:a[0]

6 6 One 4-bit full-adder

7 7 Big Picture We know how to compute functions on numbers (Sep. 4) –Any table of 0s and 1s can be interpreted as a truth table –Any truth table can be converted into a boolean function How do we control which parts of the circuit get used?

8 8 Need for control

9 9 Multiplexer Chooses one output from n inputs Real-life examples?

10 10 Multiplexer truth table

11 11 Karnaugh map for multiplexer

12 12 Putting it together

13 13 Multiplexers and selectors Multiplexer 2 n data inputs n control bits 1 output Selector no data inputs n control bits 2 n outputs Aka “demultiplexer” or “decoder”

14 14 Implementation of 2-way selector

15 15 4-way selector

16 16 Implementation of 4-way selector

17 17

18 18 Big Picture We know how to compute functions on numbers We know how to control which parts of the circuit get used How do we implement memory?


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