1. Chandrasekhar 1 MAPLD 2005/204 Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM based FPGAs Vikram Chandrasekhar, Sk. Noor Mahammad, V. Muralidharan Dr. V. Kamakoti Department of Computer Science and Engineering Indian Institute of Technology Madras, India Dr. N. Vijaykrishnan Department of Computer Science and Engineering Pennsylvania State University, U.S.A. MAPLD 2005 BOF - L

2. Chandrasekhar 2 MAPLD 2005/204 Outline of the talk ● Single Event Upsets (SEUs) in FPGAs ● Motivation ● Sensitivity of LUTs – use in SEU mitigation ● Duplication instead of TMR ● Fault simulation ● Experimental Results ● Conclusions MAPLD 2005

3. Chandrasekhar 3 MAPLD 2005/204 Single Event Upsets (SEUs) Circuit errors caused due to excess charge carriers induced primarily by external radiations In an FPGA, an SRAM configuration bit is upset – a net is forced to an erroneous value The upset remains till the circuit is reconfigured MAPLD 2005

4. Chandrasekhar 4 MAPLD 2005/204 Motivation Standard TMR design takes 200% extra area All redundancy optimizations at LUT-level not at gate-level Technology mapping changes circuit and removes redundancy Certain LUTs do not let SEUs through – need not TMR them MAPLD 2005

5. Chandrasekhar 5 MAPLD 2005/204 Insensitivity of LUTs Extension of gate sensitivity to LUTs An SEU changes a single input of an LUT Certain LUT outputs are mostly not affected by a change in the input address These are insensitive LUTs

6. Chandrasekhar 6 MAPLD 2005/204 Using insensitive LUTs Insensitive LUTs SEU-stoppers Opposite set of LUTs – sensitive LUTs Triplicate any chain of sensitive LUTs between any two insensitive LUTs Voter at the end of the three sensitive LUT chains

7. Chandrasekhar 7 MAPLD 2005/204 Using insensitive LUTs SEU inside a chain - voted out at the end of the chain SEU at an insensitive LUT - stopped at the next insensitive LUT SEU at an insensitive LUT at the last level can propagate to a primary output So all last level insensitive LUTs TMRed

8. Chandrasekhar 8 MAPLD 2005/204 How to identify insensitive LUTs ? A common technique - signal probability propagation Signal probability (SP) – prob. of a line taking a value ‘1’ Assign SPs to all PIs and propagate SPs through the circuit For an LUT, SP = Prob. of a cell storing ‘1’ being accessed However, SP values spread over entire 0-1 range Very difficult to fix a threshold for the SPs

9. Chandrasekhar 9 MAPLD 2005/204 Fault simualation Use fault simulation to identify sensitive LUTs Simulate 10,000 faults for a circuit, each with random PI LUT outputs which differ from normal values – sensitive LUTs Threshold for number of times an LUT output changed, out of 10,000 – user defined Simple but accurate technique

10. Chandrasekhar 10 MAPLD 2005/204 Duplication instead of TMR Insensitive LUTs outputs have a most probable value (MPV) Insensitive LUT at last level – need not be triplicated Store the MPV in the unused flip-flop of one LUT Use asynchronous set/reset to initialize flip-flop Connect the two LUTs and flip-flops to the voter Only possible for combinational circuits

11. Chandrasekhar 11 MAPLD 2005/204 Duplication instead of TMR Last level Insensitive LUT Last level Insensitive LUT VOTERVOTER MPV No clock Asynchronous set/reset

12. Chandrasekhar 12 MAPLD 2005/204 Experimental Results RTMR implemented on the combinational MCNC benchmark circuits 1000 faults applied to each circuit each with its own random PI assignment MAPLD 2005

13. Chandrasekhar 13 MAPLD 2005/204 Area overheads of RTMR vs. TMR 13 72224773690spla 733714121750seq 2124423941064ex5p 1386612384575pdc 1727235091397misex3 6838506911591des 029743491878apex2 729592811522alu4 No.of faults propagated No. of LUTs in RTMR circuit No.of faults propagated No. of LUTs in original circuit Benchmark Circuit MAPLD 2005 Additional redundancy 94.42 58.36 141.99 94.92 89.31 129.51 92.63 95.72

14. Chandrasekhar 14 MAPLD 2005/204 Conclusion and future work On an average, only 98.61 % additional redundancy is required compared to 200% of TMR Almost no loss of SEU immunity in RTMR Future work will concern hardening of sequential circuits against SEUs MAPLD 2005