1. Digitization at Feed Through Wu, Jinyuan Fermilab Feb. 2010

2. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov2 Introduction  There is a desire of digitizing as close to the front-end as possible:  To improve noise performance and  To permit longer cable run.  Digitization at the feed through has been considered before but there are two primary concerns:  Power consumption/cooling.  Difficulty of serving the cards at feed through.  In this document, the option of digitization at the feed through is revisited with the concerns above kept in mind.

3. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov3 The Single Slope ADC ADC Feed Through FPGA V REF Shaper Line Driver ADCShaper ADCShaper ADCShaper FPGA TDC Line Driver Line Driver Line Driver Feed Through Shaper TDC Shaper TDC Shaper TDC Analog signal of each channel from the shaper is fed to a comparator and compared with a common ramping reference voltage V REF. Pulses, rather than analog signals are transmitted on the cable. The times of transitions representing input voltage values are digitized by TDC blocks inside FPGA. This approach sometimes is (mistakenly) refereed as “Wilkinson ADC”. T1T1 V1V1 T2T2 V2V2

4. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov4 Single Slope ADC Test: Waveform Digitization Raw Data Input Waveform, Overlap Trigger & Reference Voltage Calibrated FPGA TDC 50 1000pF 100 V REF Shown here is a demo of a 6-bit single slope TDC. Sampling rate in this test is 22 MHz. Both leading and trailing reference ramps are used in this example. Nonlinear reference ramping is OK. The measurement can be calibrated.

5. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov5  With sampling rate at 2 MHz, the whole ramping cycle is 500 ns.  Arrange 409.6 ns for upward ramping.  To achieve 12-bit ADC precision, the TDC LSB is (409.6 ns)/4096 = 100 ps.  TDC with 100 ps LSB can be comfortably implemented in FPGA today. TDC Resolution Requirement T1T1 V1V1 T2T2 V2V2 500 ns

6. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov6 Noise Margin Comparison ADC Feed Through FPGA V REF Shaper Line Driver Shaper FPGA TDC Feed Through Shaper TDC Shaper TDC Shaper TDC The noise to cause an LSB error at input of 12-bit ADC is (full range)/4096, i.e., (1V+1V)/4096 = 0.5 mV. The TDC timing error can be created by differential noise on the input LVDS wires. Recall that the voltage swing of LVDS is 350 mV + 350 mV and assume the LVDS rise time is worsen to 10 ns due to attenuation of the cable. The noise to cause an LSB error (100 ps) in TDC is (350+350)*(100ps/10ns) mV = 7 mV.

7. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov7 FPGA TDC A possible choice of the TDC can be a delay line based architecture called the Wave Union TDC implemented in FPGA. Shown here is an ASIC-like implementation in a 144-pin device. 18 Channels (16 regular channels + 2 timing reference channels). This FPGA cost $28, $1.75/channel. (AD9222: $5.06/channel) LSB ~ 60 ps. RMS resolution < 25 ps. Power consumption 1.3W, or 81 mW/channel. (AD9222: 90 mW/channel) In CLK Wave Union Launcher A

8. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov8 The Option I V REF Shaper FPGA TDC Feed Through Shaper TDC Shaper TDC Shaper TDC Each line driver card at feed through now hosts 32 shapers, 32 comparators and a common ramp reference voltage generation circuit. There is no control logic on board. Amount of service is minimized. Cabling: 32 differential pairs/card or 1 pair/channel, which is the same as the baseline design. The number of connections to the digital section will be unchanged.

9. FPGA Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov9 The Option II V REF Shaper FPGA Feed Through Shaper TDC Each line driver card at feed through now hosts 32 shapers, the common ramp reference voltage generation circuit and 2 FPGA devices each having 16 TDC channels. Comparators can be absorbed into FPGA using the differential input receivers. Each FPGA serving 16 channels sends data out of 4 LVDS differential pairs in a Cat-5 RJ-45 cable (the same cable for Ethernet). Data rate for each LVDS pair is 160 M bits/s for uncompressed continuous waveform. Cabling: 8 differential pairs/card or (1 pair)/(4 channels), which is 1/4 of the baseline design. The number of connections to the digital board is now reduced from 64 pairs to 16 pairs. If necessary, a digital board now may handle 256 channels.

10. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov10 Risk Control  The digitization at feed through approach is not risk free.  The current baseline design will still be baseline.  The R&D can be done on one feed through.  The M&S cost will be controlled within 10% of the total shaper/ADC card cost. Nov 4-5-6 2009CD-1 Readiness Directors Review10

11. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov11 Why do we want to take this risk?  The digitization at feed through approach is a good study for possibilities to improve noise performance, to allow longer cable run and to reduce cost for MicroBooNE.  The cold ASIC for DUSEL or LBNE will host ADC and data compression. The R&D of digitization at feed through can be useful experience for the cold ASIC. For example, it is useful to know how to place functions that traditionally need computer access for register setting, monitoring and diagnosis in remote and inaccessible locations. Nov 4-5-6 2009CD-1 Readiness Directors Review11

12. Feb 2010Wu Jinyuan, Fermilab, jywu168@fnal.gov12 The End Thanks