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Lab 07 :Converting an older IC technology drill machine to VHDL: Slide 2 Slide 3 Generate a Truth Table from an Equation Generate a Truth Table from a.

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Presentation on theme: "Lab 07 :Converting an older IC technology drill machine to VHDL: Slide 2 Slide 3 Generate a Truth Table from an Equation Generate a Truth Table from a."— Presentation transcript:

1 Lab 07 :Converting an older IC technology drill machine to VHDL: Slide 2 Slide 3 Generate a Truth Table from an Equation Generate a Truth Table from a Diagram: Slide 4 Generate an Equation from a Diagram:

2 Lab 07 :Generate a Truth Table from an Equation Example : Generate a Truth Table for … Step 1: Generate a truth table with a wide area for the output response. 1 1 1 1 0 0 0 0 XACB 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 Step 2: Generate a column for each product term. Start with the first P-term and ignore the large inversion bar. Analyze the P-term and fill in the column. Place a 1 where A is high and B is high and C is low. 1 Fill in the remaining rows with 0’s. 0 0 0 0 0 0 0 Generate a column for the second P-term. Although the second term uses a + operator it is treated as a P- term because of the large inversion bar. Once again ignore the large inversion bar. Analyze the P-term and fill in the column. Place a 1 where A is high or C is low. 1 1 1 1 1 1 Fill in the remaining columns with 0’s. 0 0 Step 3: Generate columns to include the inversion bars. Invert each bit from the original column. 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 Step 4: OR the two columns to generate column X. For each row X is 1 if any column =1. 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 0 0 1 0 1 1 Slide #2

3 Lab 07 :Generate a Truth Table from a Diagram. To generate a Truth Table from a logic diagram you need to insert each entry of the truth table onto the logic diagram and work out the response of the system. Z X Y XYZ 00 01 10 11 Start with entry X,Y = 0,0. Work out the logic level response, at each gate, from the input side to the output. 0 0 1 0 1 11 Next entry X,Y = 0,1. Work out the logic level response, at each gate, from the input side to the output. 1 0 0 0 0 0 0 Next entry X,Y = 1,0. Work out the logic level response, at each gate, from the input side to the output. 1 0 1 1 1 1 Last entry X,Y = 1,1. Work out the logic level response, at each gate, from the input side to the output. 0 1 0 1 1 0 0 0 Slide #3

4 Lab 07 : Generate an Equation From a Diagram Work directly on the diagram and write a partial equation at the output of each gate. Work from the input side towards the output. Place a bracket around each partial equation generated. A B C X Thus X= Slide #4


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