1. Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee [M2] Huffman Encoder Project Presentation #3 February 7 th, 2007 Overall Project Objective: Design a Low Power Huffman Encoder

2. Design Proposal Chip Architecture Behavioral Verilog Implementation Size estimates/floorplanning Behavioral Verilog simulated Gate Level Design Component Layout/Simulation Chip Layout Complete Simulation Huffman Encoder Project Status

3. Implement Huffman compression portion of GZIP on a single chip Provide fast & energy efficient compression for network devices About … Huffman Encoder Project

4. Based on the DEFLATE algorithm, which is a combination of LZ77 and Huffman coding Widely used in the HTTP/1.1 protocol and general purpose data compression GZIP software compression speed(100 Mbits per second) What is GZIP? Huffman Encoder Project

5. Currently in Market: AHA362-PCIX 3.0 Gbits/sec GZIP Compression/Decompression Accelerator PCI-X, 64-bit, 133 MHz edge card interface Ideal for SAN servers, virtual tape emulation backup and recovery systems Huge, power hungry, require built-in processor

6. Huffman Encoder Project Our Target Market Network Server, on chip solution for network card and motherboard Portable Devices

7. Huffman Encoder Project Design Constraints Clock Speed >= 133MHz Hard to get benchmark for size and power in the market Optimize for power once speed constraint is met

8. Huffman Encoder Project Detailed Block Diagram from Week 2

9. Huffman Encoder Project Design Decision (week 3) Add MemSelect module Add TraverseAddr module Serial Output

10. Huffman Encoder Project

14. Serial Output

15. Huffman Encoder Project MemSelectFrequencyGroup

16. Huffman Encoder Project MemSelectLengthCode

17. Huffman Encoder Project Transistor Count (week 2) SRAM (Freq / Group)~ 4,000 SRAM (Code / Length)~ 7,000 Adders~ 1,000 Comparators~ 1,000 FSM Control Logic~ 1,000 Registers~ 1,000 Buffer~ 2,000 Others (mux, demux, etc.)~ 4,000 Total~21,000

18. Huffman Encoder Project Updated Transistor Count SRAM (Freq / Group)~ 4,000 SRAM (Code / Length)~ 7,000 CountFrequency~ 650 Find2Least~ 2,500 Combine~ 1,530 TraverseAddr~ 440 SerialOutput~ 1,300 MemSelect~ 1,370 FSM Control~ 500 Total~19,290

19. Huffman Encoder Project Initial Floorplan Frequency/Group SRAM MemSelect Length/Code MemSelect Frequency/Group Traverse Addr Traverse Addr Find2Least Combine CountFrequency Code/Length SRAM FSM Control SerialOutput

20. Huffman Encoder Project Behavioral Verilog `include "SRAM_freqGroup.v" ` include "countFreq.v" `include "control.v" module top(input clk, reset, en, start, done, input [4:0] dataIn, output ERR); wire [20:0]freqGroup, freqGroup1, freqGroup2; wire [3:0] enPhase, resetPhase; controlcontrol1(clk, reset, start, done, findReady, combineReady, oneGroupLeft, finish, enPhase, resetPhase); SRAM_freqGroupSRAM_freqGroup1(re, we, clk, reset, dataIn, freqGroup); countFreqcountFreq1(clk, reset, start, freqGroup[20:5], freqGroup[4:0], re, we, ERR); find2Freqfind2Freq1(freqGroup1, freqGroup2, freqGroupIn, ready, clk, reset, en); endmodule module topT(output reg clk, reset, en, start, done, output reg [4:0] dataIn, input ERR); always #10 clk = ~clk; initial begin $monitor($time,, "clk=%b, reset=%b, dataIn=%b, ERR=%b", clk, reset, dataIn, ERR); clk = 0; reset = 0; done = 0; en = 0; #20; reset = 1; #20; reset = 0; start = 1; dataIn = 5'b01101; #10; en = 1; // enPhase[0] should be on at time = 50 #10; dataIn = 5'b01111; #40; dataIn = 5'b01101; #40; dataIn = 5'b11001; #80; dataIn = 5'b01111; #80; $finish; end endmodule

21. Huffman Encoder Project Behavioral Verilog Simulation Waveform

22. Huffman Encoder Project Problems Timing Issues Multiple Clocks???