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Electrical Characteristics of Logic Gates
Presentation #4: Interfacing TTL and CMOS Mod January 2008 Paul R. Godin
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Interfacing CMOS and TTL
Although CMOS and TTL device families have different electrical characteristics, they can be interfaced. Fanout and Noise Margin are characteristics that must be accounted for in the design process. Propagation delay and power are other important considerations.
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CMOS TO TTL
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CMOS TTL Noise Margin Calculation
CMOS 4011B: VOH: 4.95 V VOL: 0.05 V TTL 74LS04 VIH: 2V VIL: 0.8V
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CMOS TTL Noise Margin Calculation
CMOS 4011B: VOH: 4.95 V VOL: 0.05 V TTL 74LS04 VIH: 2V VIL: 0.8V
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CMOS TTL Noise Margin Calculation
With a VnH of +2.95V and a VnL of +0.75V, there are no noise margin problems with this circuit design. Minimum=4.95V CMOS Minimum=2.0V TTL Maximum=0.8V Maximum=0.05V Output Input
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CMOS TTL Fanout Calculation
CMOS 4011B: IOH: -0.51mA IOL: 0.51mA TTL 74LS04 IIH: 20A IIL: -0.4mA
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CMOS TTL Fanout Calculation
Worst-case = 1 gate input
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CMOS TTL Fanout Calculation
Most CMOS devices can drive at least 1 TTL input from either the voltage or current perspective. Read the introduction in the specification sheet for the CMOS device.
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TTL to CMOS
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TTL CMOS Noise Margin Calculation
TTL 74LS04 VOH: 2.7V VOL: 0.5V CMOS 4011B: VIH: 3.5 V VIL: 1.5 V
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TTL CMOS Noise Margin Calculation
TTL 74LS04 VOH: 2.7V VOL: 0.5V CMOS 4011B: VIH: 3.5 V VIL: 1.5 V Voltage Problem
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TTL CMOS Noise Margin Calculation
There is a problem with the noise margin. Minimum=3.5V CMOS Minimum=2.7V TTL Maximum=1.5V Maximum=0.5V Output Input
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TTL CMOS Noise Margin Problem
The VOH of the TTL gate is too low for the CMOS gate to reliable determine a high input.
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In-Class Discussion Interface Circuits: Improve Current
Improve Noise Margin Shift Voltages Switch Loads Operate with positive and negative logic Dealing with LED Loads (review)
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Conclusion When mixing logic families, it is important to:
review the specification sheets make the necessary calculations to ensure the devices will function properly utilize interfacing devices if needed
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Review Questions What is the difference between: How do we determine:
Loading and Sinking inputs Driving and Sourcing inputs Fanout and Noise Margin ICC and ICCH IDD and IT How do we determine: Fanout IC Power Consumption Noise Margin
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End Paul R. Godin gmail.com
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