1. CSE477 L03 MOS Transistor.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 03: MOS Transistor Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477www.cse.psu.edu/~mji www.cse.psu.edu/~cg477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

2. CSE477 L03 MOS Transistor.2Irwin&Vijay, PSU, 2003 Course Administration  Instructor:Mary Jane Irwin mji@cse.psu.edu www.cse.psu.edu/~mji 227 Pond Lab Office Hrs: T 16:00-17:00 & W 9:30-10:45 mji@cse.psu.edu www.cse.psu.edu/~mji  TA:Feihui LiGreg Link feli@cse.psu.edu link@cse.psu.edu 128 Hammond226 Pond Lab Office Hrs: TBDTBD feli@cse.psu.edulink@cse.psu.edu  Labs: Accounts on 101 Pond Lab machines  URL: www.cse.psu.edu/~cg477  Text: Digital Integrated Circuits, 2 nd Edition Rabaey et. al., ©2003  Slides:pdf on the course web page after lecture

3. CSE477 L03 MOS Transistor.3Irwin&Vijay, PSU, 2003 Review: Fundamental Design Metrics  Functionality l Found On First Spin ICs/ASICs: -Functional Logic Error###################### 43% -Analog Tuning Issue########## 20% -Signal Integrity Issue######### 17% -Clock Scheme Error####### 14% -Reliability Issue###### 12% -Mixed Signal Problem##### 11% -Uses Too Much Power##### 11% -Has Path(s) Too Slow##### 10% -Has Path(s) Too Fast##### 10% -IR Drop Issues#### 7% -Firmware Error## 4% -Other Problem # 3% -Overall 61% of New ICs/ASICs Require At Least One Re-Spin -Source: Aart de Geus, Chairman & CEO of Synopsys  Costs (NRE (fixed) and RE (variable) costs)  Reliability, robustness  Performance (speed (delay) and power consumption)  Time-to-market

4. CSE477 L03 MOS Transistor.4Irwin&Vijay, PSU, 2003 Review: Reverse Bias Diode  The ideal diode equation (for both forward and reverse- bias conditions) is I D = I S (e V D /  T – 1) where V D is the voltage applied to the junction l a forward-bias lowers the potential barrier allowing carriers to flow across the diode junction l a reverse-bias raises the potential barrier and the diode becomes nonconducting  T = kT/q = 26mV at 300K I S is the saturation current of the diode + - VDVD I D (mA) V D (V)

5. CSE477 L03 MOS Transistor.5Irwin&Vijay, PSU, 2003 Review: Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G

6. CSE477 L03 MOS Transistor.6Irwin&Vijay, PSU, 2003 The MOS Transistor Polysilicon Aluminum

7. CSE477 L03 MOS Transistor.7Irwin&Vijay, PSU, 2003 The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers Gate oxide n+ SourceDrain p substrate Bulk (Body) p+ stopper Field-Oxide (SiO 2 ) n+ Polysilicon Gate L W

8. CSE477 L03 MOS Transistor.8Irwin&Vijay, PSU, 2003 Switch Model of NMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | < | V T | | V GS | > | V T | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) R on

9. CSE477 L03 MOS Transistor.9Irwin&Vijay, PSU, 2003 Switch Model of PMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | > | V DD – | V T | || V GS | < | V DD – |V T | | Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’) R on

10. CSE477 L03 MOS Transistor.10Irwin&Vijay, PSU, 2003 Threshold Voltage Concept S D p substrate B G V GS + - n+ depletion region n channel The value of V GS where strong inversion occurs is called the threshold voltage, V T

11. CSE477 L03 MOS Transistor.11Irwin&Vijay, PSU, 2003 The Threshold Voltage V T = V T0 +  (  |-2  F + V SB | -  |-2  F |) where V T0 is the threshold voltage at V SB = 0 and is mostly a function of the manufacturing process l Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. V SB is the source-bulk voltage  F = -  T ln(N A /n i ) is the Fermi potential (  T = kT/q = 26mV at 300K is the thermal voltage; N A is the acceptor ion concentration; n i  1.5x10 10 cm -3 at 300K is the intrinsic carrier concentration in pure silicon)  =  (2q  si N A )/C ox is the body-effect coefficient (impact of changes in V SB ) (  si =1.053x10 -10 F/m is the permittivity of silicon; C ox =  ox /t ox is the gate oxide capacitance with  ox =3.5x10 -11 F/m)

12. CSE477 L03 MOS Transistor.12Irwin&Vijay, PSU, 2003 The Body Effect V BS (V) V T (V) l V SB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) l A negative bias causes V T to increase from 0.45V to 0.85V

13. CSE477 L03 MOS Transistor.13Irwin&Vijay, PSU, 2003 Transistor in Linear Mode S D B G n+ Assuming V GS > V T V GS V DS IDID x V(x) -+ The current is a linear function of both V GS and V DS

14. CSE477 L03 MOS Transistor.14Irwin&Vijay, PSU, 2003 Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron)  When V DS  V GS – V T I D = k’ n W/L [(V GS – V T )V DS – V DS 2 /2] where k’ n =  n C ox =  n  ox /t ox = is the process transconductance parameter (  n is the carrier mobility (m 2 /Vsec)) k n = k’ n W/L is the gain factor of the device For small V DS, there is a linear dependence between V DS and I D, hence the name resistive or linear region

15. CSE477 L03 MOS Transistor.15Irwin&Vijay, PSU, 2003 Transistor in Saturation Mode S D B G V GS V DS > V GS - V T IDID V GS - V T -+ n+ Pinch-off Assuming V GS > V T V DS The current remains constant (transistor saturates)

16. CSE477 L03 MOS Transistor.16Irwin&Vijay, PSU, 2003 Voltage-Current Relation: Saturation Mode For long channel devices  When V DS  V GS – V T I D ’ = k’ n /2 W/L [(V GS – V T ) 2 ] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS – V T  However, the effective length of the conductive channel is modulated by the applied V DS, so I D = I D ’ (1 + V DS ) where is the channel-length modulation (varies with the inverse of the channel length)

17. CSE477 L03 MOS Transistor.17Irwin&Vijay, PSU, 2003 Current Determinates  For a fixed V DS and V GS (> V T ), I DS is a function of l the distance between the source and drain – L l the channel width – W l the threshold voltage – V T l the thickness of the SiO 2 – t ox l the dielectric of the gate insulator (e.g., SiO 2 ) –  ox l the carrier mobility -for nfets:  n = 500 cm 2 /V-sec -for pfets:  p = 180 cm 2 /V-sec

18. CSE477 L03 MOS Transistor.18Irwin&Vijay, PSU, 2003 Long Channel I-V Plot (NMOS) I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.43V

19. CSE477 L03 MOS Transistor.19Irwin&Vijay, PSU, 2003 Long Channel I-V Plot (NMOS) I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V LinearSaturation V DS = V GS - V T Quadratic dependence NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.43V cut-off 0.57V1.07V2.07V 1.57V

20. CSE477 L03 MOS Transistor.20Irwin&Vijay, PSU, 2003 Short Channel Effects  (V/  m)  n (m/s)  sat =10 5 Constant velocity Constant mobility (slope =  ) l For an NMOS device with L of.25  m, only a couple of volts difference between D and S are needed to reach velocity saturation c= c= l Behavior of short channel device mainly due to l Velocity saturation – the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) 5

21. CSE477 L03 MOS Transistor.21Irwin&Vijay, PSU, 2003 Voltage-Current Relation: Velocity Saturation For short channel devices  Linear: When V DS  V GS – V T I D =  (V DS ) k’ n W/L [(V GS – V T )V DS – V DS 2 /2] where  (V) = 1/(1 + (V/  c L)) is a measure of the degree of velocity saturation  Saturation: When V DS = V DSAT  V GS – V T I DSat =  (V DSAT ) k’ n W/L [(V GS – V T )V DSAT – V DSAT 2 /2]

22. CSE477 L03 MOS Transistor.22Irwin&Vijay, PSU, 2003 Velocity Saturation Effects Long channel devices Short channel devices V DSAT V GS -V T l V DSAT < V GS – V T so the device enters saturation before V DS reaches V GS – V T and operates more often in saturation For short channel devices and large enough V GS – V T l I DSAT has a linear dependence wrt V GS so a reduced amount of current is delivered for a given control voltage V GS = V DD

23. CSE477 L03 MOS Transistor.23Irwin&Vijay, PSU, 2003 Short Channel I-V Plot (NMOS) I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V Linear dependence NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.43V Early Velocity Saturation LinearSaturation

24. CSE477 L03 MOS Transistor.24Irwin&Vijay, PSU, 2003 MOS I D -V GS Characteristics V GS (V) I D (A) long-channel quadratic short-channel linear l Linear (short-channel) versus quadratic (long- channel) dependence of I D on V GS in saturation l Velocity-saturation causes the short- channel device to saturate at substantially smaller values of V DS resulting in a substantial drop in current drive (for V DS = 2.5V, W/L = 1.5) X 10 -4

25. CSE477 L03 MOS Transistor.25Irwin&Vijay, PSU, 2003 Short Channel I-V Plot (PMOS) I D (A) V DS (V) X 10 -4 V GS = -1.0V V GS = -1.5V V GS = -2.0V V GS = -2.5V PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V l All polarities of all voltages and currents are reversed

26. CSE477 L03 MOS Transistor.26Irwin&Vijay, PSU, 2003 The MOS Current-Source Model V T0 (V)  (V 0.5 ) V DSAT (V)k’(A/V 2 ) (V -1 ) NMOS0.430.40.63115 x 10 -6 0.06 PMOS-0.4 -30 x 10 -6 -0.1 SD G B IDID I D = 0 for V GS – V T  0 I D = k’ W/L [(V GS – V T )V min –V min 2 /2](1+ V DS ) for V GS – V T  0 with V min = min(V GS – V T, V DS, V DSAT ) and V GT = V GS - V T l Determined by the voltages at the four terminals and a set of five device parameters

27. CSE477 L03 MOS Transistor.27Irwin&Vijay, PSU, 2003 Other (Submicon) MOS Transistor Concerns  Velocity saturation  Subthreshold conduction (aka weak inversion) l Transistor is already partially conducting for voltages below V T  Threshold variations l In long-channel devices, the threshold is a function of the length (for low V DS ) l In short-channel devices, there is a drain-induced threshold barrier lowering (DIBL) at the upper end of the V DS range (for small L)  Parasitic resistances l resistances associated with the source and drain contacts  Latch-up S G D RSRS RDRD

28. CSE477 L03 MOS Transistor.28Irwin&Vijay, PSU, 2003 Subthreshold Conductance I D (A) V GS (V) 10 -12 10 -2 Subthreshold exponential region Quadratic region Linear region VTVT l Transition from ON to OFF is gradual (decays exponentially) l Current roll-off (slope factor) is also affected by increase in temperature S = n (kT/q) ln (10) (typical values 60 to 100 mV/decade) l Has repercussions in dynamic circuits and for power consumption I D ~ I S e (qV GS /nkT) where n  1

29. CSE477 L03 MOS Transistor.29Irwin&Vijay, PSU, 2003 Subthreshold I D vs V GS V DS from 0 to 0.5V I D = I S e (qV GS /nkT) (1 - e –(qV DS /kT) )(1 + V DS )

30. CSE477 L03 MOS Transistor.30Irwin&Vijay, PSU, 2003 Subthreshold I D vs V DS V GS from 0 to 0.3V I D = I S e (qV GS /nkT) (1 - e –(qV DS /kT) )(1 + V DS )

31. CSE477 L03 MOS Transistor.31Irwin&Vijay, PSU, 2003 Threshold Variations V T L Low V DS threshold Threshold varies as a function of the length of the transistor (for low V DS ) For short channel devices, the threshold varies as a function of V DS - drain-induced barrier lowering (DIBL) V DS V T Long channel threshold

32. CSE477 L03 MOS Transistor.32Irwin&Vijay, PSU, 2003 DIBL  For high V DS, the drain depletion region interacts with the source near the channel surface lowering the source potential barrier. The source then injects carriers into the channel without the gate playing a role.  DIBL is enhanced at higher V DS and shorter L. I D (A) V GS (V) 10 -12 10 -2 increasing V DS

33. CSE477 L03 MOS Transistor.33Irwin&Vijay, PSU, 2003 Next Time: The CMOS Inverter V DD V out CLCL V in

34. CSE477 L03 MOS Transistor.34Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l CMOS inverter – a static view -Reading assignment – Rabaey, et al, 5.1-5.3  Reminders l HW1 due September 16 th (next class!) l Project team and title due September 18 th l Evening midterm exam scheduled -Monday, October 20 th, 20:15 to 22:15, Location TBD -Please let me know ASAP (via email) if you have a conflict