1. Feedback from HPK Y. Unno (KEK) for HPK and ATLAS-J Silicon collaboration 2014/12/11, Y. Unno1

2. Request for Feedback from RD53 RD53: – ATLAS and CMS pixel ASIC R&D for HL-LHC – 50 x 50 µm 2 pixels Requests for feedback – Bump grid (staggering at the sensor or at the chip ?) – Bump dimensions – Dimensions of prototype / chip-array for 2015 and 2016 Specific preference / constrains for their designs. Summary slides - ideas are welcome for the discussion. 2014/12/11, Y. Unno2

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4. Feedback from HPK Bump grid (staggering at the sensor or at the chip ?) – Bump grid at the center of the 50 x 50 µm 2 pixels. Need symmetric space around the bump pad for 50 x 50 µm 2 pixels, for routing the polysilicon bias resistor, e.g. – 25 x 100 µm 2 pixels: bump grid staggering at the sensor. This has been under testing with HPK PPS sensors with ATLAS FE-I4 ASIC. Bump dimensions (Sensors) – Passivation opening: 20 µm dia. for 50 x 50 µm 2 (the larger the better) 12 µm dia. for 25 x 100 µm 2 (due to spatial issue) – Metal under passivation: 30 µm (dia.) for 50 x 50 µm 2 22 µm (dia.) for 25 x 100 µm 2 or, bump opening + ≥ 5 µm Dimensions of prototype / chip-array for 2015 and 2016 – FE-I4 size (e.g. ~2 x 2 cm 2 ) or smaller (e.g. ~1 x 1 cm 2 ) 2014/12/11, Y. Unno4

5. Feedback from HPK Specific preference / constrains for their designs. – Need symmetric space around the bump pad for 50 x 50 µm 2 pixels for routing the polysilicon bias resistor, e.g. – Fiducial marks at the corners of chip for automated alignment. – P.S. If AC-coupling is to be tried, can the AC-coupling capacitor be implemented on the pixels at the chip? 2014/12/11, Y. Unno5

6. Fiducial Marks at Corners These marks are for the pattern recognition of the alignment in the bumpbonding. 2014/12/11, Y. Unno6

7. Summary Feedback from HPK. – Bump grid at the center of 50 x 50 µm 2 pixels. – 25 x 100 µm 2 pixels: bump grid staggering at the sensor. – Fiducial marks at the corners of the chip. 2014/12/11, Y. Unno7